JPS57173944A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS57173944A
JPS57173944A JP5953881A JP5953881A JPS57173944A JP S57173944 A JPS57173944 A JP S57173944A JP 5953881 A JP5953881 A JP 5953881A JP 5953881 A JP5953881 A JP 5953881A JP S57173944 A JPS57173944 A JP S57173944A
Authority
JP
Japan
Prior art keywords
oxide film
openings
film
thermal oxide
etched
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5953881A
Other languages
Japanese (ja)
Inventor
Shigeru Morita
Norio Endo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP5953881A priority Critical patent/JPS57173944A/en
Publication of JPS57173944A publication Critical patent/JPS57173944A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting

Abstract

PURPOSE:To reduce the area necessitating for the margin to compensate for precision of manufacture of openings of a semiconductor device by a method wherein two layers having different etching speeds are laminated, and selective etchings are performed on the respective layers independently by two time etching processes to form the openings. CONSTITUTION:A field oxide film 22 is formed on a p type silicon substrate 21, openings parts are provided selectively, and a source region 25 and drain region 26 are formed. Then a thermal oxide film 28, polycrystalline silicon film 29, and CVD oxide film 30 to be used as an insulating layer are formed on the whole surface. Then a photo resist film 31 for formation of contact holes is formed on the CVD oxide film. The CVD oxide film 30 is etched using ammonium fluoride liquid, and the polycrystalline silicon layer 29 is etched in succession according to the plasma etching method using Freon gas. Then after thermal oxide films 32 are formed on the end faces on the respective sides of the contact holes, the thermal oxide film 28 is removed using the ammonium fluoride liquid, and electrodes 33, 34 are formed.
JP5953881A 1981-04-20 1981-04-20 Manufacture of semiconductor device Pending JPS57173944A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5953881A JPS57173944A (en) 1981-04-20 1981-04-20 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5953881A JPS57173944A (en) 1981-04-20 1981-04-20 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS57173944A true JPS57173944A (en) 1982-10-26

Family

ID=13116137

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5953881A Pending JPS57173944A (en) 1981-04-20 1981-04-20 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS57173944A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61292323A (en) * 1985-04-02 1986-12-23 ソーン、イーエムアイ、ノース、アメリカ、インコーポレーテッド Formation of contact window in semiconductor structure

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5277589A (en) * 1975-12-24 1977-06-30 Hitachi Ltd Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5277589A (en) * 1975-12-24 1977-06-30 Hitachi Ltd Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61292323A (en) * 1985-04-02 1986-12-23 ソーン、イーエムアイ、ノース、アメリカ、インコーポレーテッド Formation of contact window in semiconductor structure

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