JPS57150197A - Storage circuit - Google Patents

Storage circuit

Info

Publication number
JPS57150197A
JPS57150197A JP56034799A JP3479981A JPS57150197A JP S57150197 A JPS57150197 A JP S57150197A JP 56034799 A JP56034799 A JP 56034799A JP 3479981 A JP3479981 A JP 3479981A JP S57150197 A JPS57150197 A JP S57150197A
Authority
JP
Japan
Prior art keywords
bit information
memory
decoder
circuit
written
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56034799A
Other languages
English (en)
Inventor
Tsuneo Mano
Junzo Yamada
Junichi Inoue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP56034799A priority Critical patent/JPS57150197A/ja
Priority to US06/356,041 priority patent/US4460998A/en
Priority to GB8206917A priority patent/GB2097621B/en
Priority to FR8204011A priority patent/FR2501891B1/fr
Priority to NL8200978A priority patent/NL8200978A/nl
Priority to CA000398170A priority patent/CA1172768A/en
Priority to DE19823208763 priority patent/DE3208763A1/de
Publication of JPS57150197A publication Critical patent/JPS57150197A/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/18—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits
    • G06F11/183—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits by voting, the voting not being performed by the redundant components
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/18—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/74—Masking faults in memories by using spares or by reconfiguring using duplex memories, i.e. using dual copies
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Dram (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Static Random-Access Memory (AREA)
JP56034799A 1981-03-11 1981-03-11 Storage circuit Pending JPS57150197A (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
JP56034799A JPS57150197A (en) 1981-03-11 1981-03-11 Storage circuit
US06/356,041 US4460998A (en) 1981-03-11 1982-03-08 Semiconductor memory devices
GB8206917A GB2097621B (en) 1981-03-11 1982-03-09 Semiconductor memory devices
FR8204011A FR2501891B1 (fr) 1981-03-11 1982-03-10 Memoire semi-conductrice autocorrectrice d'erreurs
NL8200978A NL8200978A (nl) 1981-03-11 1982-03-10 Halfgeleidergeheugeninrichtingen.
CA000398170A CA1172768A (en) 1981-03-11 1982-03-11 Semiconductor memory devices
DE19823208763 DE3208763A1 (de) 1981-03-11 1982-03-11 Halbleiter-speichereinrichtung

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56034799A JPS57150197A (en) 1981-03-11 1981-03-11 Storage circuit

Publications (1)

Publication Number Publication Date
JPS57150197A true JPS57150197A (en) 1982-09-16

Family

ID=12424282

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56034799A Pending JPS57150197A (en) 1981-03-11 1981-03-11 Storage circuit

Country Status (7)

Country Link
US (1) US4460998A (ja)
JP (1) JPS57150197A (ja)
CA (1) CA1172768A (ja)
DE (1) DE3208763A1 (ja)
FR (1) FR2501891B1 (ja)
GB (1) GB2097621B (ja)
NL (1) NL8200978A (ja)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4562576A (en) * 1982-08-14 1985-12-31 International Computers Limited Data storage apparatus
JPS59121699A (ja) * 1982-12-28 1984-07-13 Toshiba Corp 冗長性回路変更装置
JPS59144098A (ja) * 1983-02-08 1984-08-17 Fujitsu Ltd 半導体記憶装置
US4587638A (en) * 1983-07-13 1986-05-06 Micro-Computer Engineering Corporation Semiconductor memory device
US4584682A (en) * 1983-09-02 1986-04-22 International Business Machines Corporation Reconfigurable memory using both address permutation and spare memory elements
JPS60191500A (ja) * 1984-03-08 1985-09-28 Sharp Corp 冗長回路
US4622668A (en) * 1984-05-09 1986-11-11 International Business Machines Corporation Process and apparatus for testing a microprocessor and dynamic ram
JPS6150293A (ja) * 1984-08-17 1986-03-12 Fujitsu Ltd 半導体記憶装置
JPS61264599A (ja) * 1985-05-16 1986-11-22 Fujitsu Ltd 半導体記憶装置
JPH07118193B2 (ja) * 1986-09-18 1995-12-18 富士通株式会社 半導体記憶装置
US5103169A (en) * 1989-11-15 1992-04-07 Texas Instruments Incorporated Relayless interconnections in high performance signal paths
US5307142A (en) * 1991-11-15 1994-04-26 The United States Of America As Represented By The United States Department Of Energy High performance static latches with complete single event upset immunity
US6222762B1 (en) * 1992-01-14 2001-04-24 Sandisk Corporation Multi-state memory
DE19525149A1 (de) * 1995-07-11 1997-01-16 Telefunken Microelectron Verfahren zum selbsttätigen Erkennen und Korrigieren eines ungültigen Datensatzes und System zu seiner Durchführung
US6226233B1 (en) * 1996-07-30 2001-05-01 Seagate Technology, Inc. Magneto-optical system utilizing MSR media
US5940549A (en) * 1996-07-30 1999-08-17 Seagate Technology, Incorporated Optical system and method using optical fibers for storage and retrieval of information
US6574015B1 (en) 1998-05-19 2003-06-03 Seagate Technology Llc Optical depolarizer
DE10120670B4 (de) * 2001-04-27 2008-08-21 Qimonda Ag Verfahren zur Reparatur von Hardwarefehlern in Speicherbausteinen
KR100418522B1 (ko) * 2001-06-11 2004-02-14 삼성전자주식회사 이동가능한 스페어 메모리 어레이 어드레스를 갖는 불휘발성 반도체 메모리 장치 및 그에 따른 리드방법
JP2007257791A (ja) * 2006-03-24 2007-10-04 Fujitsu Ltd 半導体記憶装置
JP4918824B2 (ja) * 2006-08-18 2012-04-18 富士通株式会社 メモリコントローラおよびメモリ制御方法
US20080077840A1 (en) * 2006-09-27 2008-03-27 Mark Shaw Memory system and method for storing and correcting data
JP2008236311A (ja) * 2007-03-20 2008-10-02 Fujitsu Ltd 伝送装置
US20080282120A1 (en) * 2007-05-11 2008-11-13 Macronix International Co., Ltd. Memory structure, repair system and method for testing the same
US20090125790A1 (en) * 2007-11-13 2009-05-14 Mcm Portfolio Llc Method and Apparatus of Automatically Selecting Error Correction Algorithms by a NAND Flash Controller
US8020053B2 (en) * 2008-10-29 2011-09-13 Hewlett-Packard Development Company, L.P. On-line memory testing
US10671497B2 (en) * 2018-01-19 2020-06-02 International Business Machines Corporation Efficient and selective sparing of bits in memory systems

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3434116A (en) * 1966-06-15 1969-03-18 Ibm Scheme for circumventing bad memory cells
US3544777A (en) * 1967-11-06 1970-12-01 Trw Inc Two memory self-correcting system
US3898443A (en) * 1973-10-29 1975-08-05 Bell Telephone Labor Inc Memory fault correction system
GB1491702A (en) * 1975-04-01 1977-11-16 Int Computers Ltd Memory systems
US4093985A (en) * 1976-11-05 1978-06-06 North Electric Company Memory sparing arrangement
US4228528B2 (en) * 1979-02-09 1992-10-06 Memory with redundant rows and columns
JPS6051749B2 (ja) * 1979-08-31 1985-11-15 富士通株式会社 エラ−訂正方式

Also Published As

Publication number Publication date
US4460998A (en) 1984-07-17
CA1172768A (en) 1984-08-14
NL8200978A (nl) 1982-10-01
FR2501891B1 (fr) 1988-09-09
GB2097621A (en) 1982-11-03
DE3208763A1 (de) 1982-11-04
GB2097621B (en) 1985-07-03
FR2501891A1 (fr) 1982-09-17

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