JPS57112021A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS57112021A
JPS57112021A JP55187308A JP18730880A JPS57112021A JP S57112021 A JPS57112021 A JP S57112021A JP 55187308 A JP55187308 A JP 55187308A JP 18730880 A JP18730880 A JP 18730880A JP S57112021 A JPS57112021 A JP S57112021A
Authority
JP
Japan
Prior art keywords
layer
pattern
mask
positioning
circumferential region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55187308A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6135693B2 (https=
Inventor
Shuzo Fujimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55187308A priority Critical patent/JPS57112021A/ja
Priority to US06/331,477 priority patent/US4423127A/en
Priority to EP81110535A priority patent/EP0061536B1/en
Priority to DE8181110535T priority patent/DE3170209D1/de
Publication of JPS57112021A publication Critical patent/JPS57112021A/ja
Publication of JPS6135693B2 publication Critical patent/JPS6135693B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7073—Alignment marks and their environment
    • G03F9/7084—Position of mark on substrate, i.e. position in (x, y, z) of mark, e.g. buried or resist covered mark, mark on rearside, at the substrate edge, in the circuit area, latent image mark, marks in plural levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/101—Marks applied to devices, e.g. for alignment or identification characterised by the type of information, e.g. logos or symbols
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/501—Marks applied to devices, e.g. for alignment or identification for use before dicing

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
JP55187308A 1980-12-29 1980-12-29 Manufacture of semiconductor device Granted JPS57112021A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP55187308A JPS57112021A (en) 1980-12-29 1980-12-29 Manufacture of semiconductor device
US06/331,477 US4423127A (en) 1980-12-29 1981-12-16 Method of manufacturing a semiconductor device
EP81110535A EP0061536B1 (en) 1980-12-29 1981-12-17 Method of manufacturing a semiconductor device having improved alignment marks and alignment marks for said method
DE8181110535T DE3170209D1 (en) 1980-12-29 1981-12-17 Method of manufacturing a semiconductor device having improved alignment marks and alignment marks for said method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55187308A JPS57112021A (en) 1980-12-29 1980-12-29 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS57112021A true JPS57112021A (en) 1982-07-12
JPS6135693B2 JPS6135693B2 (https=) 1986-08-14

Family

ID=16203722

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55187308A Granted JPS57112021A (en) 1980-12-29 1980-12-29 Manufacture of semiconductor device

Country Status (4)

Country Link
US (1) US4423127A (https=)
EP (1) EP0061536B1 (https=)
JP (1) JPS57112021A (https=)
DE (1) DE3170209D1 (https=)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6336033U (https=) * 1986-08-22 1988-03-08
WO1999056308A1 (en) * 1998-04-28 1999-11-04 Nikon Corporation Exposure system and method of manufacturing micro device
KR100352836B1 (ko) * 1995-12-15 2002-12-16 주식회사 하이닉스반도체 반도체 소자의 중첩 정밀도 측정 마크

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3336901A1 (de) * 1983-10-11 1985-04-18 Deutsche Itt Industries Gmbh, 7800 Freiburg Maskenmarkierung und substratmarkierung fuer ein verfahren zum justieren einer eine maskenmarkierung enthaltenden photomaske auf einer substratmarkierung
JPS62108206A (ja) * 1985-11-06 1987-05-19 Canon Inc カラ−フィルタ−の製造方法
GB8803171D0 (en) * 1988-02-11 1988-03-09 English Electric Valve Co Ltd Imaging apparatus
GB8806232D0 (en) * 1988-03-16 1988-04-13 Plessey Co Plc Vernier structure for flip chip bonded devices
JP2754609B2 (ja) * 1988-06-08 1998-05-20 日本電気株式会社 半導体装置の製造方法
JP3118899B2 (ja) * 1991-10-01 2000-12-18 日本電気株式会社 アライメントチェックパターン
US5503959A (en) * 1991-10-31 1996-04-02 Intel Corporation Lithographic technique for patterning a semiconductor device
US5407763A (en) * 1992-05-28 1995-04-18 Ceridian Corporation Mask alignment mark system
US5450109A (en) * 1993-03-24 1995-09-12 Hewlett-Packard Company Barrier alignment and process monitor for TIJ printheads
US5316984A (en) * 1993-03-25 1994-05-31 Vlsi Technology, Inc. Bright field wafer target
JP3693370B2 (ja) * 1994-10-18 2005-09-07 株式会社ルネサステクノロジ 重合わせ精度測定マーク
JP3420391B2 (ja) * 1995-06-20 2003-06-23 キヤノン株式会社 電気回路基板におけるアライメントマーク構造
EP0841594A3 (en) 1996-11-07 1999-08-25 Nikon Corporation Mark for position detection, mark detecting method and apparatus, and exposure system
US6102516A (en) * 1997-03-17 2000-08-15 Lexmark International, Inc. Fiducial system and method for conducting an inspection to determine if a second element is properly aligned relative to a first element
US6228743B1 (en) 1998-05-04 2001-05-08 Motorola, Inc. Alignment method for semiconductor device
EP1221065A2 (en) * 1999-07-22 2002-07-10 Koninklijke Philips Electronics N.V. Display device substrate with alignment markers
US6612159B1 (en) * 1999-08-26 2003-09-02 Schlumberger Technologies, Inc. Overlay registration error measurement made simultaneously for more than two semiconductor wafer layers
US6498640B1 (en) * 1999-12-30 2002-12-24 Koninklijke Philips Electronics N.V. Method to measure alignment using latent image grating structures
US6856029B1 (en) * 2001-06-22 2005-02-15 Lsi Logic Corporation Process independent alignment marks
DE10137105A1 (de) * 2001-07-30 2003-02-27 Infineon Technologies Ag Halbleiteranordnung, Verfahren zum Herstellen einer solchen sowie Verwendung von Messmarken einer solchen
TW200407995A (en) * 2002-11-08 2004-05-16 Nanya Technology Corp Mark and method for multiple alignment
JP2005101150A (ja) * 2003-09-24 2005-04-14 Renesas Technology Corp アライメントマークの形成方法
US7737534B2 (en) * 2008-06-10 2010-06-15 Northrop Grumman Systems Corporation Semiconductor devices that include germanium nanofilm layer disposed within openings of silicon dioxide layer
KR101136973B1 (ko) * 2008-12-11 2012-04-19 한국전자통신연구원 통합 보안 장치 및 통합 보안 방법
AT12737U1 (de) * 2010-09-17 2012-10-15 Austria Tech & System Tech Verfahren zum herstellen einer aus mehreren leiterplattenbereichen bestehenden leiterplatte sowie leiterplatte
US9953806B1 (en) 2015-03-26 2018-04-24 Doug Carson & Associates, Inc. Substrate alignment detection using circumferentially extending timing pattern
WO2016154539A1 (en) 2015-03-26 2016-09-29 Doug Carson & Associates, Inc. Substrate alignment through detection of rotating tming pattern
US10134624B2 (en) 2015-03-26 2018-11-20 Doug Carson & Associates, Inc. Substrate alignment detection using circumferentially extending timing pattern
US9806031B2 (en) * 2015-04-22 2017-10-31 United Microelectronics Corp. Monitor method for process control in a semiconductor fabrication process
JP6414141B2 (ja) * 2016-05-31 2018-10-31 日亜化学工業株式会社 発光装置
CN109856930B (zh) * 2017-11-30 2021-05-25 京东方科技集团股份有限公司 对准标记、基板及其制作方法、曝光对准方法
CN109141237B (zh) * 2018-08-20 2020-10-13 武汉华星光电半导体显示技术有限公司 一种检测器件的误测判断的方法及装置
CN113534626B (zh) * 2020-04-14 2024-07-16 中国科学院微电子研究所 用于套刻精度测量的标记系统及量测方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3617267A (en) * 1969-04-24 1971-11-02 Itek Corp Process for forming a series of masters in register
US3783520A (en) * 1970-09-28 1974-01-08 Bell Telephone Labor Inc High accuracy alignment procedure utilizing moire patterns
GB1501158A (en) * 1974-05-13 1978-02-15 Siemens Ag Production of multilayer structures in semiconductor chip
JPS5534442A (en) * 1978-08-31 1980-03-11 Fujitsu Ltd Preparation of semiconductor device
US4309813A (en) * 1979-12-26 1982-01-12 Harris Corporation Mask alignment scheme for laterally and totally dielectrically isolated integrated circuits

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6336033U (https=) * 1986-08-22 1988-03-08
KR100352836B1 (ko) * 1995-12-15 2002-12-16 주식회사 하이닉스반도체 반도체 소자의 중첩 정밀도 측정 마크
WO1999056308A1 (en) * 1998-04-28 1999-11-04 Nikon Corporation Exposure system and method of manufacturing micro device
US6416912B1 (en) 1998-04-28 2002-07-09 Nikon Corporation Method of manufacturing microdevice utilizing combined alignment mark

Also Published As

Publication number Publication date
JPS6135693B2 (https=) 1986-08-14
DE3170209D1 (en) 1985-05-30
EP0061536A1 (en) 1982-10-06
US4423127A (en) 1983-12-27
EP0061536B1 (en) 1985-04-24

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