JPS5685855A - Semiconductor memory element - Google Patents
Semiconductor memory elementInfo
- Publication number
- JPS5685855A JPS5685855A JP16255879A JP16255879A JPS5685855A JP S5685855 A JPS5685855 A JP S5685855A JP 16255879 A JP16255879 A JP 16255879A JP 16255879 A JP16255879 A JP 16255879A JP S5685855 A JPS5685855 A JP S5685855A
- Authority
- JP
- Japan
- Prior art keywords
- region
- type
- film
- semiconductor region
- storage unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/33—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor extending under the transistor
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
PURPOSE:To form a dynamic RAM in a high density by burying a charge storage unit forming a semiconductor memory cell under a transistor region, thereby forming the cell in a streoscopic structure and reducing the area. CONSTITUTION:An N type first semiconductor region 4 is diffused as a charge storage unit on a P type Si substrate 2, and is surrounded by a field SiO2 film 6 to form it in a floating state. Subsequently, a P type second semiconductor region 8 is epitaxially grown in a floating state to become a channel region on the surface layer of the region 4, an N type third semiconductor region 12 transferred from polycrystalline Si or amorphous Si is formed through an interlayer isolating SiO2 insulating film 10 formed on the bottom surface adjacent thereto, and they are used as the source and drain regions of a transistor. Thereafter a thin SiO2 film 14 are covered on the regions 8 and 12, and gate electrodes 16 are mounted from the upper portion of the region 8 to the side thereof with the film 14 as a gate insulating film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16255879A JPS5685855A (en) | 1979-12-14 | 1979-12-14 | Semiconductor memory element |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16255879A JPS5685855A (en) | 1979-12-14 | 1979-12-14 | Semiconductor memory element |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5685855A true JPS5685855A (en) | 1981-07-13 |
JPS6353700B2 JPS6353700B2 (en) | 1988-10-25 |
Family
ID=15756862
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16255879A Granted JPS5685855A (en) | 1979-12-14 | 1979-12-14 | Semiconductor memory element |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5685855A (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5350985A (en) * | 1976-10-20 | 1978-05-09 | Fujitsu Ltd | Semiconductor memory device |
-
1979
- 1979-12-14 JP JP16255879A patent/JPS5685855A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5350985A (en) * | 1976-10-20 | 1978-05-09 | Fujitsu Ltd | Semiconductor memory device |
Also Published As
Publication number | Publication date |
---|---|
JPS6353700B2 (en) | 1988-10-25 |
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