JPS5648133A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5648133A
JPS5648133A JP12356779A JP12356779A JPS5648133A JP S5648133 A JPS5648133 A JP S5648133A JP 12356779 A JP12356779 A JP 12356779A JP 12356779 A JP12356779 A JP 12356779A JP S5648133 A JPS5648133 A JP S5648133A
Authority
JP
Japan
Prior art keywords
substrate
electrode
wires
heat treatment
diffusion layers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12356779A
Other languages
Japanese (ja)
Inventor
Katsunobu Yoshimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP12356779A priority Critical patent/JPS5648133A/en
Publication of JPS5648133A publication Critical patent/JPS5648133A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To prevent variations in device characteristics by making an electrode for substrate bias with a material having easier ohmic contact with a substrate than an interior wiring material connected to diffusion layers on a semiconductor substrate wherein each component is ohmically connected by heat treatment. CONSTITUTION:Al wires 5 with Si are formed on a source and a drain on an Si substrate. The Al with Si around a scribed line section and the neighborhood is removed. Next, an electrode 7 for substrate bias by pure Al is made around the scribed line and the neighborhood. Next, heat treatment is applied at about 500 deg.C and for about 30min to complete ohmic contact with the wires 5 and diffusion layers 2 and that with the electrode 7 and the substrate 1. Wires 5 and the electrode 7 are covered with SiO2 8. The substrate has a low impurity concentration compared to the diffusion layers. Therefore, ohmic connection is normally hard to obtain. However, with pure Al used, each component will be ohmically connected together with interior wires by heat treatment under the same condition. Therefore, satisfactory ohmic connection will be obtained without deteriorating device characteristics.
JP12356779A 1979-09-26 1979-09-26 Manufacture of semiconductor device Pending JPS5648133A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12356779A JPS5648133A (en) 1979-09-26 1979-09-26 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12356779A JPS5648133A (en) 1979-09-26 1979-09-26 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5648133A true JPS5648133A (en) 1981-05-01

Family

ID=14863770

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12356779A Pending JPS5648133A (en) 1979-09-26 1979-09-26 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5648133A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4945685A (en) * 1972-09-04 1974-05-01
JPS5210673A (en) * 1975-07-15 1977-01-27 Matsushita Electronics Corp Manufacturing method of silicon semi-conductor device
JPS52123872A (en) * 1976-04-12 1977-10-18 Toshiba Corp Semiconductor device and its production

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4945685A (en) * 1972-09-04 1974-05-01
JPS5210673A (en) * 1975-07-15 1977-01-27 Matsushita Electronics Corp Manufacturing method of silicon semi-conductor device
JPS52123872A (en) * 1976-04-12 1977-10-18 Toshiba Corp Semiconductor device and its production

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