JPS5645018A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5645018A
JPS5645018A JP12102179A JP12102179A JPS5645018A JP S5645018 A JPS5645018 A JP S5645018A JP 12102179 A JP12102179 A JP 12102179A JP 12102179 A JP12102179 A JP 12102179A JP S5645018 A JPS5645018 A JP S5645018A
Authority
JP
Japan
Prior art keywords
film
surface stabilizing
semiconductor device
interelement
polycrystal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12102179A
Other languages
Japanese (ja)
Other versions
JPS6154250B2 (en
Inventor
Naoyuki Tsuda
Hajime Kawamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP12102179A priority Critical patent/JPS5645018A/en
Publication of JPS5645018A publication Critical patent/JPS5645018A/en
Publication of JPS6154250B2 publication Critical patent/JPS6154250B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02373Group 14 semiconducting materials
    • H01L21/02381Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02439Materials
    • H01L21/02441Group 14 semiconducting materials
    • H01L21/0245Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02494Structure
    • H01L21/02496Layer structure
    • H01L21/0251Graded layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02494Structure
    • H01L21/02513Microstructure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02532Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02587Structure
    • H01L21/0259Microstructure
    • H01L21/02595Microstructure polycrystalline

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Formation Of Insulating Films (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To improve a semiconductor device in electrostatic burnout characteristics and to uniform the interelement characteristics by using a polycrystalline Si film and a mono-to-polycrystal transition region as a surface stabilizing film. CONSTITUTION:On a monocrystalline Si substrate 1, a polycrystalline Si film 4 is provided as a surface stabilizing film, and moreover a mono-to-polycrystal transition region 5 is provided between the substrate 1 and the film 4. The structure having the film 4 and the region 5 as a surface stabilizing film permits the electrostatic burnout characteristics to be largely improved and at the same time, the interelement characteristics to be uniformed. In addition, the preparation of the element is provided with excellent controllability, and thus the reproducibility of the element characteristics can be greatly improved.
JP12102179A 1979-09-20 1979-09-20 Semiconductor device Granted JPS5645018A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12102179A JPS5645018A (en) 1979-09-20 1979-09-20 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12102179A JPS5645018A (en) 1979-09-20 1979-09-20 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS5645018A true JPS5645018A (en) 1981-04-24
JPS6154250B2 JPS6154250B2 (en) 1986-11-21

Family

ID=14800838

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12102179A Granted JPS5645018A (en) 1979-09-20 1979-09-20 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5645018A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5734374A (en) * 1980-08-08 1982-02-24 Mitsubishi Electric Corp Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5734374A (en) * 1980-08-08 1982-02-24 Mitsubishi Electric Corp Semiconductor device
JPS6328345B2 (en) * 1980-08-08 1988-06-08 Mitsubishi Electric Corp

Also Published As

Publication number Publication date
JPS6154250B2 (en) 1986-11-21

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