JPS6328345B2 - - Google Patents
Info
- Publication number
- JPS6328345B2 JPS6328345B2 JP55109936A JP10993680A JPS6328345B2 JP S6328345 B2 JPS6328345 B2 JP S6328345B2 JP 55109936 A JP55109936 A JP 55109936A JP 10993680 A JP10993680 A JP 10993680A JP S6328345 B2 JPS6328345 B2 JP S6328345B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- amorphous silicon
- sio
- silicon film
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 21
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 20
- 239000001257 hydrogen Substances 0.000 claims description 13
- 229910052739 hydrogen Inorganic materials 0.000 claims description 13
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 12
- 229910052731 fluorine Inorganic materials 0.000 claims description 9
- 239000011737 fluorine Substances 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 8
- 230000000087 stabilizing effect Effects 0.000 claims description 6
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 claims 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 14
- 230000004888 barrier function Effects 0.000 description 14
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 8
- 230000015556 catabolic process Effects 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 230000005684 electric field Effects 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- 239000000969 carrier Substances 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 230000000704 physical effect Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000005424 photoluminescence Methods 0.000 description 1
- 238000005546 reactive sputtering Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Description
【発明の詳細な説明】
この発明は、高耐圧化をはかつた半導体装置に
関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device with high breakdown voltage.
一般の半導体装置において、逆方向耐圧は１つ
の性能指数である。素子の高耐圧化を阻害する要
因として半導体表面の接合が曲面接合を持ち、か
つSiO2等の半導体表面安定化膜と半導体基板と
の表面に共有結合ボンドの切れた表面準位が介在
して、半導体表面での空乏層の伸びが抑制される
ことがあげられる。 In general semiconductor devices, reverse breakdown voltage is one figure of merit. One of the factors that hinders the ability of devices to achieve high breakdown voltages is that the semiconductor surface has a curved surface junction, and that there are surface states with broken covalent bonds on the surface of the semiconductor surface stabilizing film such as SiO 2 and the semiconductor substrate. , the growth of the depletion layer on the semiconductor surface is suppressed.
周知のように、シヨツトキバリヤタイプダイオ
ードは少数キヤリヤの蓄積効果がないために、高
速動作が可能であることが知られている。 As is well known, shot barrier type diodes are known to be capable of high speed operation because they do not have the effect of accumulating minority carriers.
第１図はシヨツトキバリヤダイオードの基本的
な構成を示す断面図で、１は半導体基板、２はシ
ヨツトキバリヤメタル、３は電極である。通常、
清浄な共有結合半導体の表面は、ボンドが切れた
状態、すなわちダングリングボンドが露出してお
り、このダングリングボンドによる表面準位は、
表面原子数と同程度であり、高密度である。この
表面準位のおよぼすシヨツトキバリヤダイオード
への影響は下記のとおりである。 FIG. 1 is a cross-sectional view showing the basic structure of a shot barrier diode, in which 1 is a semiconductor substrate, 2 is a shot barrier metal, and 3 is an electrode. usually,
On the surface of a clean covalently bonded semiconductor, the bonds are broken, that is, dangling bonds are exposed, and the surface states due to these dangling bonds are
The number of atoms is about the same as that of the surface, and the density is high. The influence of this surface level on the shot barrier diode is as follows.
ｎ型半導体の場合、表面準位の数と、ドナー
の数を比較すると圧倒的に表面準位の数が多
く、従つてドナーの数が少々変化しても占有さ
れた表面準位の最高エネルギー位置（フエルミ
準位）はほとんど変化しない。いわゆるフエル
ミレベルピンニング効果が起きやすい。 In the case of n-type semiconductors, when comparing the number of surface states and the number of donors, the number of surface states is overwhelmingly large. Therefore, even if the number of donors changes slightly, the highest energy of the occupied surface states The position (Fermi level) hardly changes. The so-called Fermi level pinning effect is likely to occur.
この表面準位によつて逆バイアス時の接合周
辺部の空乏層の伸びがおさえられるために表面
での電界強度が大きくなり逆方向耐圧が低下す
る。 This surface level suppresses the expansion of the depletion layer around the junction during reverse bias, increasing the electric field strength at the surface and lowering the reverse breakdown voltage.
第２図ａ〜ｃは従来のシヨツトキバリヤタイプ
素子を高耐圧化するために行われている種々の構
成を示す断面図で、第２図ａはシヨツトキバリヤ
接合周辺部に用いる半導体基板１と逆の伝導性を
持つ領域となるガードリング５を挿入することに
よつて、周辺部の電界集中を緩和するとともに、
このガードリング５の外部は、例えばSiO2膜４
等によつて覆うことにより、なにもない半導体結
晶表面は半導体の表面準位よりもさらに表面準位
を下げるようにしようという試みであるが、通常
このようなｐ−ｎ接合を持つガードリング５を挿
入したときに、ｐ−ｎ接合とシヨツトキバリヤ接
合の並列動作となるため、ｐ−ｎ接合部での少数
キヤリヤの注入、蓄積効果により動作周波数が低
下するので、シヨツトキバリヤ素子の利点を生か
しきれない。第２図ｂは、SiO2膜４による表面
準位の低減と、図中のＡ部のフイルドプレートに
よつて空乏層の伸びを大きくしようという試みの
もの、また、第２図ｃは、半導体基板１をあらか
じめエツチングして接合面に、図中のＢ部のカー
バーチヤ（曲率）を持たして電界集中を緩和しよ
うという試みのものである。 Figures 2a to 2c are cross-sectional views showing various configurations used to increase the voltage resistance of conventional shot barrier type devices. By inserting the guard ring 5, which becomes a conductive region, electric field concentration in the peripheral area is alleviated, and
The outside of this guard ring 5 is covered with, for example, a SiO 2 film 4.
This is an attempt to lower the surface level of the bare semiconductor crystal surface further than the surface level of the semiconductor by covering it with a guard ring such as a p-n junction. When 5 is inserted, the p-n junction and the shot barrier junction operate in parallel, so the operating frequency decreases due to the injection and accumulation effect of minority carriers at the p-n junction, so the advantages of the shot barrier element cannot be fully utilized. do not have. Figure 2b shows an attempt to reduce the surface state by using the SiO 2 film 4 and increase the extension of the depletion layer by using the field plate shown in section A in the figure. This is an attempt to reduce the electric field concentration by etching the substrate 1 in advance to give the bonding surface a curvature (section B in the figure).
このように上記構造に共通していることとして
接合周辺部にSiO2膜４等を用いるプレーナ技術
を応用しようということであるが、Si表面を
SiO2化することによつて素子のパツシベーシヨ
ン効果とともにSiのダングリングボンドと酸素の
結合によつて若干の表面準位（界面準位）の低減
には有効であるが、本来の半導体材料の逆方向耐
圧（例えばメサ構造ダイオードのアバランシエブ
レークダウン電圧）までの向上は難かしい。 In this way, the common feature of the above structures is the application of planar technology that uses a SiO 2 film 4 etc. around the junction, but the Si surface is
By converting to SiO 2 , it is effective to reduce the surface level (interface level) slightly due to the passivation effect of the device and the bond between the dangling bonds of Si and oxygen, but it is the opposite of the original semiconductor material. It is difficult to improve the directional breakdown voltage (for example, the avalanche breakdown voltage of a mesa structure diode).
この発明は上記の点にかんがみなされたもの
で、表面安定化膜として水素、弗素等を含むアモ
ルフアスシリコンを用いて、特に曲面接合の影響
が大きいシヨツトキバリヤダイオードの高耐圧化
を図つたものである。以下、この発明について説
明する。 This invention was made in consideration of the above points, and aims to increase the withstand voltage of shot barrier diodes, which are particularly affected by curved surface junctions, by using amorphous silicon containing hydrogen, fluorine, etc. as a surface stabilizing film. It is. This invention will be explained below.
第３図はこの発明の一実施例を示す高耐圧シヨ
ツトキバリヤダイオードの断面図である。第３図
において、第１図、第２図と同一符号は同一また
は相当部分を示し、６は水素もしくは弗素を含む
アモルフアスシリコン膜である。 FIG. 3 is a sectional view of a high voltage shot barrier diode showing an embodiment of the present invention. In FIG. 3, the same reference numerals as in FIGS. 1 and 2 indicate the same or corresponding parts, and 6 is an amorphous silicon film containing hydrogen or fluorine.
このように、半導体基板１の上部にアモルフア
スシリコン膜６を生成し、その上部に直接シヨツ
トキバリヤメタル２および電極３を形成する方法
で、電極３の周辺部に空乏層の伸びを大きくする
ために、水素もしくは弗素を含むアモルフアスシ
リコン膜６を用いることを特徴とするものであ
る。水素を含む雰囲気中での反応性スパツタリン
グで成長したアモルフアスシリコン膜６あるいは
比較的低温100〜400℃でのSiH4ガスあるいは
SiF4ガスのグロー放電法で作成したアモルフアス
シリコン膜６では、この膜中に水素あるいは弗素
が含まれており、これらの水素、弗素がアモルフ
アスシリコン膜６（例えば蒸着等で作成した膜）
特有の膜中ダングリングボンド（共有結合の切れ
た部分）に結合して、このダングリングボンドを
消滅させ、バンド内局在準位密度が1016〜1017／
cm3・eV程度まで減少可能になることが知られて
いる。すなわち水素、弗素を含むアモルフアスシ
リコン膜６を半導体表面のダングリングボンドを
消滅させることに利用するものである。 In this way, by forming the amorphous silicon film 6 on the top of the semiconductor substrate 1 and directly forming the shot barrier metal 2 and the electrode 3 on top of the amorphous silicon film 6, the extension of the depletion layer around the electrode 3 is increased. For this purpose, an amorphous silicon film 6 containing hydrogen or fluorine is used. Amorphous silicon film 6 grown by reactive sputtering in an atmosphere containing hydrogen or SiH 4 gas grown at a relatively low temperature of 100 to 400°C or
The amorphous silicon film 6 created by the SiF 4 gas glow discharge method contains hydrogen or fluorine, and these hydrogen and fluorine cause the amorphous silicon film 6 (for example, a film created by vapor deposition, etc.) to contain hydrogen or fluorine.
It binds to the unique dangling bonds (broken covalent bonds) in the film and annihilates these dangling bonds, increasing the localized level density within the band to 10 16 - 10 17 /
It is known that it can be reduced to about cm 3 eV. That is, the amorphous silicon film 6 containing hydrogen and fluorine is used to eliminate dangling bonds on the semiconductor surface.
水素を含むアモルフアス膜（ａ−Si：Ｈ）は、
この中のＨがSi、GaAs等の半導体表面準位を低
減させる。多結晶シリコンとａ−Si：Ｈの物性上
の相違点として、ａ−Si：Ｈは特に水素が含まれ
たことにより表面準位、あるいは未結合手による
局在準位の低減効果がある点で多結晶シリコンと
異なる。このように、水素を含むことにより、(1)
光吸収係数（バンドギヤツプエネルギー）の増
大、(2)抵抗値の増大、(3)誘電率の増加、(4)キヤリ
ヤライフタイムの増大、(5)ホトルミネセンス強度
増加等の物性的な特徴がある。これはａ−Si：Ｆ
についても同様である。 Amorphous amorphous film (a-Si:H) containing hydrogen is
Among these, H reduces the surface level of semiconductors such as Si and GaAs. The difference in physical properties between polycrystalline silicon and a-Si:H is that a-Si:H has the effect of reducing surface levels or localized levels due to dangling bonds due to the inclusion of hydrogen. different from polycrystalline silicon. In this way, by including hydrogen, (1)
Physical properties such as increase in optical absorption coefficient (band gap energy), (2) increase in resistance value, (3) increase in dielectric constant, (4) increase in carrier lifetime, and (5) increase in photoluminescence intensity. There are characteristics. This is a-Si:F
The same applies to
第４図はこの発明の他の実施例を示す断面図
で、第１図〜第３図と同一符号は同一または相当
部分を示し、電極３とアモルフアスシリコン膜６
の界面にSiO2膜４等を挿入して電極３の形成に
よつて発生する物理的ストレスを緩和するように
した構造について示したものである。 FIG. 4 is a sectional view showing another embodiment of the present invention, in which the same reference numerals as in FIGS. 1 to 3 indicate the same or corresponding parts, and the electrode 3 and the amorphous silicon film 6
This figure shows a structure in which a SiO 2 film 4 or the like is inserted at the interface of the electrode 3 to alleviate the physical stress generated by the formation of the electrode 3.
以上説明したようにこの発明は、アモルフアス
シリコン膜を半導体表面の安定化膜として用いた
ので、従来方法で用いられているSiO2膜等によ
る安定化膜と比較して次のような利点を有する。 As explained above, this invention uses an amorphous silicon film as a stabilizing film on the semiconductor surface, so it has the following advantages compared to stabilizing films such as SiO 2 films used in conventional methods. have
SiとSiO2膜の界面においては、SiO2、酸素不
足のSiO2領域、酸素添何のSi領域（Siの多い層）、
Siといつた具合に組成の連続的変化が微視的に存
在し、酸素欠乏のSiO2膜、すなわち酸素空位ま
たはSi過剰の領域がある。これらが膜中荷電体と
なり少数キヤリヤの再結合中心とか新たに
SiO2／Si界面に表面準位を形成しやすく、
SiO2／Si界面での空乏層の伸びを抑制して局部
的電界集中の要因となる。一方、アモルフアスシ
リコン膜の場合、アモルフアスシリコン膜特有の
構造柔軟性と均一性およびアモルフアスシリコン
膜生成時に発生した過剰水素や弗素の影響により
半導体基板との界面に界面準位の生成がなく理想
的な表面安定膜として利用できる。 At the interface between Si and SiO 2 films, there are SiO 2 , an oxygen-deficient SiO 2 region, an oxygen-added Si region (Si-rich layer),
Microscopically, there is a continuous change in composition such as Si, and there is an oxygen-deficient SiO 2 film, that is, a region with oxygen vacancies or Si excess. These become charged bodies in the membrane and create a new recombination center for minority carriers.
It is easy to form surface states at the SiO 2 /Si interface,
This suppresses the elongation of the depletion layer at the SiO 2 /Si interface and causes local electric field concentration. On the other hand, in the case of an amorphous silicon film, there is no generation of interface states at the interface with the semiconductor substrate due to the structural flexibility and uniformity peculiar to the amorphous silicon film and the influence of excess hydrogen and fluorine generated during the formation of the amorphous silicon film. It can be used as an ideal surface stabilizing film.
第１図はシヨツトキバリヤダイオードの基本的
な構成を示す断面図、第２図ａ〜ｃは従来行われ
ているシヨツトキバリヤタイプ素子を高耐圧化す
るための素子の構成を示す断面図、第３図はこの
発明の一実施例を示す高耐圧シヨツトキバリヤダ
イオードの断面図、第４図はこの発明の他の実施
例を示す断面図である。
図中、１は半導体基板、２はシヨツトキバリヤ
メタル、３は電極、４はSiO2膜、５はガードリ
ング、６はアモルフアスシリコン膜である。な
お、図中の同一符号は同一または相当部分を示
す。
FIG. 1 is a cross-sectional view showing the basic structure of a shot-lock barrier diode, and FIGS. 2 a to 2-c are cross-sectional views showing the structure of a conventional shot-lock barrier type device for increasing the withstand voltage. FIG. 3 is a sectional view of a high voltage shot barrier diode showing one embodiment of the invention, and FIG. 4 is a sectional view showing another embodiment of the invention. In the figure, 1 is a semiconductor substrate, 2 is a shot barrier metal, 3 is an electrode, 4 is an SiO 2 film, 5 is a guard ring, and 6 is an amorphous silicon film. Note that the same reference numerals in the figures indicate the same or corresponding parts.
Claims (1)
において、前記半導体基板の表面の接合部以外の
表面領域の安定化膜として水素あるいは弗素を含
むアモルフアスシリコン膜を用いたことを特徴と
する半導体装置。1. A semiconductor device having a junction on the surface of a semiconductor substrate, characterized in that an amorphous silicon film containing hydrogen or fluorine is used as a stabilizing film in a surface region other than the junction on the surface of the semiconductor substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10993680A JPS5734374A (en) | 1980-08-08 | 1980-08-08 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10993680A JPS5734374A (en) | 1980-08-08 | 1980-08-08 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5734374A JPS5734374A (en) | 1982-02-24 |
| JPS6328345B2 true JPS6328345B2 (en) | 1988-06-08 |
Family
ID=14522857
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10993680A Granted JPS5734374A (en) | 1980-08-08 | 1980-08-08 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5734374A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0636427B2 (en) * | 1983-02-04 | 1994-05-11 | 株式会社東芝 | Semiconductor pressure converter |
| JPS613470A (en) * | 1984-06-18 | 1986-01-09 | Nec Corp | Semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5068776A (en) * | 1973-10-23 | 1975-06-09 | ||
| JPS5645018A (en) * | 1979-09-20 | 1981-04-24 | Matsushita Electronics Corp | Semiconductor device |
-
1980
- 1980-08-08 JP JP10993680A patent/JPS5734374A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5068776A (en) * | 1973-10-23 | 1975-06-09 | ||
| JPS5645018A (en) * | 1979-09-20 | 1981-04-24 | Matsushita Electronics Corp | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5734374A (en) | 1982-02-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4431858A (en) | Method of making quasi-grain boundary-free polycrystalline solar cell structure and solar cell structure obtained thereby | |
| JP2542448B2 (en) | Field effect transistor and method of manufacturing the same | |
| US7696584B2 (en) | Reduced leakage power devices by inversion layer surface passivation | |
| US4028149A (en) | Process for forming monocrystalline silicon carbide on silicon substrates | |
| US6077760A (en) | Structure and method of manufacturing single-crystal silicon carbide/single-crystal silicon heterojunctions with negative differential resistance characteristics | |
| US4385200A (en) | Photovoltaic cell having a hetero junction of amorphous silicon carbide and amorphous silicon | |
| JPH02264475A (en) | Silicon carbode schottkey diode and its manufacture | |
| Lindholm et al. | Heavily doped polysilicon-contact solar cells | |
| US4451838A (en) | Semiconductor photoelectric conversion device | |
| KR840001605B1 (en) | Thin film transistor | |
| US3798079A (en) | Triple diffused high voltage transistor | |
| CN103000697A (en) | Silicon carbide (SiC) Schottky diode and method for manufacturing same | |
| JPH10511812A (en) | Semiconductor device having a passivation layer | |
| KR100994924B1 (en) | Solar cell and Method for manufacturing the same | |
| GB2253943A (en) | Diamond heterojunction diode | |
| Yu et al. | The junction characteristics of carbonaceous film/n‐type silicon (C/n‐Si) layer photovoltaic cell | |
| JPS6328345B2 (en) | ||
| JP3313344B2 (en) | SiC / Si heterostructure semiconductor switch and method of manufacturing the same | |
| Selim | High-voltage, large-area planar devices | |
| US3831185A (en) | Controlled inversion bistable switching diode | |
| JPS5936836B2 (en) | Amorphous thin film solar cell | |
| Hastas et al. | Structural, electrical, and low-frequency-noise properties of amorphous-carbon–silicon heterojunctions | |
| JPH05275725A (en) | Photovoltaic device and its manufacture | |
| Rittner et al. | Dependence of efficiency of shallow junction silicon solar cells on substrate doping | |
| JP3197674B2 (en) | Photovoltaic device |