JP3197674B2 - Photovoltaic device - Google Patents
Photovoltaic deviceInfo
- Publication number
- JP3197674B2 JP3197674B2 JP10500293A JP10500293A JP3197674B2 JP 3197674 B2 JP3197674 B2 JP 3197674B2 JP 10500293 A JP10500293 A JP 10500293A JP 10500293 A JP10500293 A JP 10500293A JP 3197674 B2 JP3197674 B2 JP 3197674B2
- Authority
- JP
- Japan
- Prior art keywords
- amorphous semiconductor
- film
- intrinsic amorphous
- photovoltaic device
- interface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/546—Polycrystalline silicon PV cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/547—Monocrystalline silicon PV cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/548—Amorphous silicon PV cells
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- Photovoltaic Devices (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、太陽電池や光センサ等
の光起電力装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a photovoltaic device such as a solar cell or an optical sensor.
【０００２】[0002]
【従来の技術】一般に、光起電力装置は、発電層として
用いられる半導体の種類により、単結晶系、多結晶系、
非晶質系に分類される。2. Description of the Related Art In general, a photovoltaic device has a single crystal type, a polycrystal type, and a semiconductor type depending on the type of a semiconductor used as a power generation layer.
Classified as amorphous.
【０００３】この中で、ここ数年、活発な研究開発がな
されたのが、非晶質系からなる光起電力装置である。そ
の理由として、従来の単結晶系のものと比較して、非晶
質系は大面積の形成が容易であり、かつその製造工程に
要するエネルギーが小さくてすむことなどから低コスト
が期待できたためである。[0003] In recent years, active research and development have been made on amorphous photovoltaic devices in recent years. The reason is that, compared to the conventional single crystal type, the amorphous type is easy to form a large area, and low cost can be expected because the energy required for the manufacturing process is small. It is.
【０００４】しかし、これまで多くの研究成果を得たに
もかかわらず、その性能面では単結晶系の光起電力装置
には及んでいない。[0004] However, although many research results have been obtained so far, its performance is not as good as that of a single crystal photovoltaic device.
【０００５】そこで、近年、光起電力装置の開発の新た
な試みとして、非晶質半導体と結晶系半導体（単結晶半
導体，多結晶半導体）とを組み合わせて半導体接合を形
成させることにより、それぞれの物性が持つ長所を活か
すことで、より高い光電変換効率を得る研究が進められ
ている。In recent years, as a new attempt to develop a photovoltaic device, a semiconductor junction is formed by combining an amorphous semiconductor and a crystalline semiconductor (single crystal semiconductor, polycrystalline semiconductor). Research is being conducted to obtain higher photoelectric conversion efficiency by utilizing the advantages of physical properties.
【０００６】しかし、通常、前記の各半導体を単に接触
させるだけでは、良好な半導体接合を形成することはで
きない。例えば、図５（ｂ）に示すように、ｎ型の単結
晶半導体１１とｐ型の非晶質半導体１２とを直接接触さ
せ、ｐｎ接合（ヘテロｐｎ接合）を形成したとしても、
同図（ａ）のバンドプロファイルに示すように、ホール
に対する高い障壁が形成されるため、光起電力装置とし
て十分な光電変換効率を得ることはできない。However, a good semiconductor junction cannot usually be formed simply by bringing the above-mentioned semiconductors into contact with each other. For example, as shown in FIG. 5B, even if an n-type single crystal semiconductor 11 and a p-type amorphous semiconductor 12 are brought into direct contact to form a pn junction (hetero pn junction),
As shown in the band profile of FIG. 2A, a high barrier against holes is formed, so that sufficient photoelectric conversion efficiency cannot be obtained as a photovoltaic device.
【０００７】これは、光照射により発生した半導体中の
光生成キャリアの多くが前記ｐｎ接合界面での再結合に
より失われてしまい、前記光生成キャリアを外部に取り
出せないためである。This is because most of the photogenerated carriers in the semiconductor generated by light irradiation are lost due to recombination at the pn junction interface, and the photogenerated carriers cannot be taken out.
【０００８】かかる再結合の原因は、前記非晶質半導体
の局在準位によると考えられる。即ち、非晶質半導体で
は、一般に導電型決定不純物をドーピングすることによ
り、その膜質は著しく劣化する。この影響はバンドギャ
ップ内の局在準位の増加として現れる。そして、この局
在準位は、ｐｎ接合界面に界面準位を生成するように働
きかけ、結果として前記光キャリアを再結合させること
になる。It is considered that the cause of such recombination is a localized level of the amorphous semiconductor. That is, the film quality of an amorphous semiconductor is significantly degraded by doping with impurities that determine the conductivity type. This effect appears as an increase in localized levels in the band gap. Then, the localized level acts to generate an interface level at the pn junction interface, and as a result, the photocarriers are recombined.
【０００９】そこで、本願出願人は、図６（ｂ）に示す
ように、前記のｐｎ接合を薄膜の真性非晶質半導体膜１
３を介在させて行う構造（以下、ＨＩＴ構造という。）
を有した光起電力装置を提案した（特開平４−１３０６
７１号公報参照）。これにより、ｐｎ接合界面での膜質
が良好なものとなり、界面準位密度が低下し、光生成キ
ャリアの再結合を抑制することが可能となった。即ち、
同図（ａ）に示すように、ホールに対する障壁が幾分低
くなり、従来よりも高い光電変換効率を得ることができ
る。The applicant of the present invention, as shown in FIG. 6 (b), connects the pn junction to a thin intrinsic amorphous semiconductor film 1 as shown in FIG.
3 (hereinafter referred to as HIT structure)
(Japanese Patent Laid-Open No. 4-1306)
No. 71). As a result, the film quality at the pn junction interface is improved, the interface state density is reduced, and the recombination of photogenerated carriers can be suppressed. That is,
As shown in FIG. 2A, the barrier against holes is somewhat lower, and a higher photoelectric conversion efficiency than in the prior art can be obtained.
【００１０】[0010]
【発明が解決しようとする課題】しかしながら、前記の
ＨＩＴ構造は、ｎ型の単結晶半導体膜１１に真性非晶質
半導体膜１３を接触するものであり、これが良質な膜で
あるとしても、単結晶半導体膜１１との間で異種物質界
面を形成するものであるから、この異種物質界面におい
て分子ネットワークが連続的に繋がり難いという問題は
依然として残される。即ち、格子歪みに起因する局在準
位ができるため、界面準位を十分に低減することはでき
ない。加えて、ホールに対する障壁が低くなったとは言
え、未だ残っている。However, the above-mentioned HIT structure is such that the intrinsic amorphous semiconductor film 13 is brought into contact with the n-type single crystal semiconductor film 11, and even if this is a good film, Since a heterogeneous substance interface is formed with the crystalline semiconductor film 11, the problem that the molecular network is difficult to be continuously connected at the heterogeneous substance interface still remains. That is, since a localized level is generated due to lattice distortion, the interface level cannot be sufficiently reduced. In addition, although the barrier to the hole has been lowered, it still remains.
【００１１】本発明は、上記の事情に鑑み、異種物質界
面における分子ネットワークが連続的に繋がり易くなる
ようにして界面準位を低減し、光電変換効率を向上させ
得る光起電力装置を提供することを目的とする。The present invention has been made in view of the above circumstances, and provides a photovoltaic device capable of improving the photoelectric conversion efficiency by reducing the interface state by facilitating continuous connection of the molecular networks at the interface between different substances. The purpose is to:
【００１２】[0012]
【課題を解決するための手段】本発明の光起電力装置
は、上記の課題を解決するために、互いに逆導電型の関
係を有する非晶質半導体と結晶系半導体との間に薄膜の
真性非晶質半導体を介在させた光起電力装置において、
前記の真性非晶質半導体は、シリコン・ゲルマニウムか
らなり、前記の非晶質半導体との界面側では結晶系半導
体との界面側におけるよりもゲルマニウム含有量が少な
くされていることを特徴としている。In order to solve the above-mentioned problems, a photovoltaic device according to the present invention has an intrinsic property of a thin film between an amorphous semiconductor and a crystalline semiconductor having a relationship of opposite conductivity type to each other. In a photovoltaic device with an amorphous semiconductor interposed,
The intrinsic amorphous semiconductor is made of silicon-germanium, and has a lower germanium content at the interface with the amorphous semiconductor than at the interface with the crystalline semiconductor.
【００１３】[0013]
【作用】上記の構成によれば、前記の真性非晶質半導体
はシリコン・ゲルマニウムからなるため、分子ネットワ
ークは「粗」となり、ネットワークの自由度（柔軟性）
が大きくなる。よって、異種物質界面での歪みは減少
し、分子ネットワークは連続的に繋がり易くなる。これ
により、界面準位密度が低減される。加えて、前記真性
非晶質半導体の裏面側バンドギャップＥg が結晶系半導
体のＥg に近づくため、光電変換効率が向上する。一
方、ゲルマニウムの含有量は、非晶質半導体との界面側
で少なくされているので、光入射側のＥg ＞裏面側のＥ
g 、の関係が生じ、当該真性非晶質半導体にゲルマニウ
ムが均一に含まれている場合と比較して高い電圧を得る
ことが可能となる。According to the above structure, since the intrinsic amorphous semiconductor is made of silicon germanium, the molecular network becomes "coarse" and the degree of freedom (flexibility) of the network is increased.
Becomes larger. Therefore, the strain at the heterogeneous material interface is reduced, and the molecular network is easily connected continuously. Thereby, the interface state density is reduced. In addition, the order backside bandgap E g of an intrinsic amorphous semiconductor approaches the E g of the crystalline semiconductor, the photoelectric conversion efficiency is improved. On the other hand, since the content of germanium is reduced at the interface side with the amorphous semiconductor, E g on the light incident side> E g on the back side
g , and a higher voltage can be obtained as compared with the case where germanium is uniformly contained in the intrinsic amorphous semiconductor.
【００１４】[0014]
【実施例】以下、本発明をその実施例を示す図に基づい
て説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings showing the embodiments.
【００１５】図１は、本発明の光起電力装置の断面図お
よびこれに対応付けたバンドプロファイルを示した概念
図である。FIG. 1 is a conceptual diagram showing a cross-sectional view of a photovoltaic device according to the present invention and a band profile associated therewith.
【００１６】同図（ｂ）において、１はｎ型単結晶シリ
コン基板、２は真性非晶質半導体膜、３は前記ｎ型単結
晶シリコン基板１と逆導電型となるｐ型非晶質シリコン
膜、４はｎ型単結晶シリコン基板１とコンタクトするア
ルミニウムなどからなる電極、５はＩＴＯ（Ｉｎｄｉｕ
ｍ Ｔｉｎ Ｏｘｉｄｅ）膜や酸化スズ等からなる透明
電極膜である。In FIG. 1B, reference numeral 1 denotes an n-type single crystal silicon substrate, 2 denotes an intrinsic amorphous semiconductor film, and 3 denotes p-type amorphous silicon having a conductivity type opposite to that of the n-type single crystal silicon substrate 1. The film 4 is an electrode made of aluminum or the like which is in contact with the n-type single-crystal silicon substrate 1, and 5 is ITO (Indiu).
m Tin Oxide) film or a transparent electrode film made of tin oxide or the like.
【００１７】前記の真性非晶質半導体膜２は、シリコン
（Ｓｉ）・ゲルマニウム（Ｇｅ）からなり、ゲルマニウ
ム（Ｇｅ）の含有量は、前記のｎ型単結晶シリコン基板
１との界面側（裏面側）で多くなっている。即ち、光入
射側のＧｅ／Ｓｉ＜上記界面側（裏面側）のＧｅ／Ｓ
ｉ、の関係を充たすようにしてある。また、本実施例で
は、Ｇｅ量は、上記界面側（裏面側）で対Ｓｉ比１５％
〜４０％（３０％が最適）程度としている。The intrinsic amorphous semiconductor film 2 is made of silicon (Si) / germanium (Ge), and the content of germanium (Ge) depends on the interface side (back surface) with the n-type single crystal silicon substrate 1. Side). That is, Ge / Si on the light incident side <Ge / S on the interface side (back side).
The relationship of i is satisfied. In this embodiment, the Ge amount is 15% with respect to Si on the interface side (back side).
Approximately 40% (30% is optimal).
【００１８】このように、上記真性非晶質半導体膜２が
シリコン（Ｓｉ）・ゲルマニウム（Ｇｅ）からなるの
で、上記界面側（裏面側）では真性非晶質半導体膜２の
分子ネットワークは「粗」となり、ネットワークの自由
度（柔軟性）が大きくなるため、異種物質界面での歪み
が減少し、分子ネットワークは連続的に繋がり易くな
る。これにより、界面準位密度が低減される。加えて、
上記真性非晶質半導体膜２の裏面側でのバンドギャップ
Ｅg が結晶シリコン１のＥg に近づくため、同図（ａ）
に示しているように、ホールに対する障壁が従来のＨＩ
Ｔ構造のものより低くなり、光電変換効率が向上する。As described above, since the intrinsic amorphous semiconductor film 2 is made of silicon (Si) / germanium (Ge), the molecular network of the intrinsic amorphous semiconductor film 2 is “rough” on the interface side (back side). ", And the degree of freedom (flexibility) of the network is increased, so that the strain at the interface between different materials is reduced, and the molecular networks are easily connected continuously. Thereby, the interface state density is reduced. in addition,
Since the band gap E g on the back surface side of the intrinsic amorphous semiconductor film 2 approaches the E g of the crystalline silicon 1, FIG.
As shown in FIG.
It is lower than that of the T structure, and the photoelectric conversion efficiency is improved.
【００１９】一方、ゲルマニウムの含有量は、ｐ型非晶
質シリコン膜３との界面側（光入射側）で少なくされて
いるので、当該真性非晶質半導体膜２にゲルマニウムが
均一に含まれている場合と比較して高い電圧を得ること
が可能となる。即ち、前述した、光入射側のＧｅ／Ｓｉ
＜上記界面側（裏面側）のＧｅ／Ｓｉ、の関係を充たす
ため、光入射側のＥg ＞裏面側のＥg 、の関係が生じ、
真性非晶質半導体膜２に均一にＧｅが含まれるよりも、
高い電圧が得られることになる。On the other hand, the germanium content is reduced on the interface side (light incident side) with the p-type amorphous silicon film 3, so that the intrinsic amorphous semiconductor film 2 contains germanium uniformly. It is possible to obtain a higher voltage than in the case where That is, the Ge / Si on the light incident side described above.
<Since to meet the Ge / Si, the relationship between the interface side (back side), E g of the light incident side> of the back side E g, the relationship occurs,
Rather than uniformly containing Ge in the intrinsic amorphous semiconductor film 2,
A high voltage will be obtained.
【００２０】本実施例の光起電力装置の形成方法として
は、まず、ｎ型単結晶シリコン基板１上にプラズマＣＶ
Ｄ法により真性非晶質半導体膜２を成膜する。このプラ
ズマＣＶＤによる膜形成は、基板温度２００℃、ＲＦパ
ワー１０Ｗ、反応室内圧力０．１Ｔｏｒｒの条件下で行
った。また、反応室内に供給するガスとしては、ＧｅＨ
4 ，ＳｉＨ4 ，Ｈ2 を用い、Ｈ2 の流量は１００ｓｃｃ
ｍに、ＳｉＨ4 の流量は１ｓｃｃｍに各々設定した。一
方、ＧｅＨ4 については、図２に示すように、真性非晶
質半導体膜２の成膜開始時は、流量を１ｓｃｃｍとし、
次第に少なくして、必要膜厚が得られるころに流量が０
となるように流量制御している。これにより、ｎ型単結
晶シリコン基板１との界面側でゲルマニウム（Ｇｅ）を
多く含む真性非晶質半導体膜２が形成される。また、上
述のようにゲルマニウム（Ｇｅ）量を一定の勾配で徐々
に少なくすることにより、真性非晶質半導体膜２におい
てグレーデッドなバンドプロファイルが得られる。As a method of forming the photovoltaic device of this embodiment, first, a plasma CV is formed on an n-type single crystal silicon substrate 1.
The intrinsic amorphous semiconductor film 2 is formed by the method D. The film formation by the plasma CVD was performed under the conditions of a substrate temperature of 200 ° C., an RF power of 10 W and a reaction chamber pressure of 0.1 Torr. The gas supplied into the reaction chamber is GeH
4 , SiH 4 , and H 2, and the flow rate of H 2 is 100 scc.
m, and the flow rate of SiH 4 was set to 1 sccm. On the other hand, as shown in FIG. 2, the flow rate of GeH 4 is set to 1 sccm at the start of the formation of the intrinsic amorphous semiconductor film 2.
Gradually reduce the flow rate until the required film thickness is obtained.
The flow rate is controlled so that Thus, an intrinsic amorphous semiconductor film 2 containing a large amount of germanium (Ge) is formed on the interface side with the n-type single crystal silicon substrate 1. As described above, a graded band profile can be obtained in the intrinsic amorphous semiconductor film 2 by gradually decreasing the amount of germanium (Ge) at a constant gradient.
【００２１】次に、同じくプラズマＣＶＤ法により、真
性非晶質半導体膜２上にｐ型非晶質シリコン膜３を堆積
する。このプラズマＣＶＤ法による膜形成は、基板温度
２００℃、ＲＦパワー１０Ｗ、反応室内圧力０．１Ｔｏ
ｒｒの条件下で行った。また、反応室内に供給するガス
としては、ＳｉＨ4 とＢ2 Ｈ6 を用い、ＳｉＨ4 の流量
は５ｓｃｃｍに設定し、Ｂ2 Ｈ6 のＳｉＨ4 に対する流
量比は５％に設定した。Next, a p-type amorphous silicon film 3 is deposited on the intrinsic amorphous semiconductor film 2 by the same plasma CVD method. The film is formed by the plasma CVD method at a substrate temperature of 200 ° C., an RF power of 10 W, and a reaction chamber pressure of 0.1 To.
Performed under rr conditions. The gases supplied into the reaction chamber were SiH 4 and B 2 H 6 , the flow rate of SiH 4 was set at 5 sccm, and the flow rate ratio of B 2 H 6 to SiH 4 was set at 5%.
【００２２】次に、光入射側となるｐ型非晶質シリコン
膜３上には透明導電膜５を形成し、ｎ型単結晶シリコン
基板１の裏面には金属電極４を形成する。Next, a transparent conductive film 5 is formed on the p-type amorphous silicon film 3 on the light incident side, and a metal electrode 4 is formed on the back surface of the n-type single crystal silicon substrate 1.
【００２３】これにより、本発明の光起電力装置が得ら
れる。Thus, the photovoltaic device of the present invention is obtained.
【００２４】図３は、前述したプラズマＣＶＤ法により
真性非晶質半導体膜２を成膜する工程において、成膜開
始時のＧｅＨ4 ／ＳｉＨ4 流量比を、０％、５０％、１
００％としたときの、その各々の条件下で得られた真性
非晶質半導体膜２を用いた光起電力装置の光電変換効率
を示したグラフである。ここで、ＧｅＨ4 ／ＳｉＨ4流
量比が０の場合とは、真性非晶質半導体膜２がゲルマニ
ウム（Ｇｅ）を含んでいない従来のＨＩＴ構造に相当す
る。このグラフから明らかなように、本発明の光起電力
装置の光電変換効率は、従来のＨＩＴ構造の光起電力装
置に比べ高くなっていることが分かる。FIG. 3 shows that the flow rate ratio of GeH 4 / SiH 4 at the start of film formation is 0%, 50%, 1% in the step of forming the intrinsic amorphous semiconductor film 2 by the above-mentioned plasma CVD method.
5 is a graph showing the photoelectric conversion efficiency of a photovoltaic device using the intrinsic amorphous semiconductor film 2 obtained under each condition when the ratio is set to 00%. Here, the case where the GeH 4 / SiH 4 flow ratio is 0 corresponds to a conventional HIT structure in which the intrinsic amorphous semiconductor film 2 does not contain germanium (Ge). As is clear from this graph, the photoelectric conversion efficiency of the photovoltaic device of the present invention is higher than that of the conventional photovoltaic device having the HIT structure.
【００２５】図４は、従来のＨＩＴ構造を有する光起電
力装置と、本発明の構造を有する光起電力装置とにおけ
る、各々の真性非晶質半導体膜２の膜厚を変化させたと
きの光電変換効率の変化を示したグラフである。このグ
ラフから分かるように、本発明の構造を有する光起電力
装置は、従来のＨＩＴ構造を有する光起電力装置より
も、有効膜厚範囲は狭くなるが、その効率の高さは、本
発明の構造を有する光起電力装置の方が高くなってい
る。また、本発明の構造では、真性非晶質半導体膜２の
膜厚が約４０Åのところで光電変換効率のピークを迎
え、真性非晶質半導体膜２の最適膜厚は従来よりも薄く
なっている。FIG. 4 shows the photovoltaic device having the conventional HIT structure and the photovoltaic device having the structure of the present invention when the thickness of each intrinsic amorphous semiconductor film 2 is changed. 5 is a graph showing a change in photoelectric conversion efficiency. As can be seen from this graph, the photovoltaic device having the structure of the present invention has a narrower effective film thickness range than the conventional photovoltaic device having the HIT structure, but the efficiency is higher than that of the present invention. The photovoltaic device having the structure described above is higher. In the structure of the present invention, the photoelectric conversion efficiency reaches a peak at a thickness of the intrinsic amorphous semiconductor film 2 of about 40 °, and the optimum thickness of the intrinsic amorphous semiconductor film 2 is smaller than the conventional thickness. .
【００２６】なお、真性非晶質半導体膜２の膜厚が或る
厚みを越えると光電変換効率が低下するのは、従来のＨ
ＩＴ構造においてもいえるものであるが、これは、真性
非晶質半導体膜２が、界面準位の低減を主な機能とし、
当該膜２自体の層中で発生する光キャリアはほとんど変
化効率に寄与せず、むしろ、変換効率の低下を引き起こ
すためと考えられる。When the thickness of the intrinsic amorphous semiconductor film 2 exceeds a certain thickness, the photoelectric conversion efficiency is reduced by the conventional H
The same can be said for the IT structure. This is because the intrinsic amorphous semiconductor film 2 has a main function of reducing interface states,
It is considered that the optical carriers generated in the layer of the film 2 itself hardly contribute to the change efficiency, but rather cause the conversion efficiency to decrease.
【００２７】また、本発明で採用する真性非晶質半導体
膜の膜厚の下限値としては、通常のプラズマＣＶＤ装置
やスパッタ装置あるいは、常圧ＣＶＤ装置などによる形
成で制御可能な数Åまでであるが、その膜厚の制御容易
性からすれば、２０Å以上が好適である。The lower limit of the thickness of the intrinsic amorphous semiconductor film employed in the present invention is up to several Å which can be controlled by a normal plasma CVD apparatus, a sputtering apparatus, or a normal pressure CVD apparatus. However, in view of the controllability of the film thickness, 20 ° or more is preferable.
【００２８】更に、ここでいう真性非晶質半導体とは、
例えば、前記のプラズマＣＶＤ法によって形成されたも
のであれば、導電型決定不純物としてのドーピングガス
を全く添加することなく形成された真性非晶質半導体を
含むことは勿論であるが、それ以外に微量のドーピング
ガスを添加して形成することにより、実質的に真性型に
制御された非晶質シリコンをも含むものである。Further, the intrinsic amorphous semiconductor referred to herein is:
For example, if it is formed by the above-mentioned plasma CVD method, it naturally includes an intrinsic amorphous semiconductor formed without adding a doping gas as a conductivity type determining impurity at all, but in addition to the above, By forming by adding a small amount of doping gas, amorphous silicon controlled to be substantially intrinsic is also included.
【００２９】非晶質シリコンなどの非晶質半導体では、
一般に不純物をなんら添加することなく形成した場合で
も、僅かではあるが導電性を顕すことがあるためで、例
えば、非晶質シリコンの場合、僅かなｎ型を示す。本発
明は、真性非晶質半導体として、このような実質的に真
性な非晶質半導体をも使用しうるものである。In an amorphous semiconductor such as amorphous silicon,
In general, even if formed without adding any impurities, conductivity may be exhibited, albeit slightly, so that amorphous silicon, for example, shows a slight n-type. The present invention can use such a substantially intrinsic amorphous semiconductor as the intrinsic amorphous semiconductor.
【００３０】また、本実施例では、結晶系半導体として
単結晶半導体を例示したが、これに限らず多結晶半導体
を用いてもよいものである。この場合においても、真性
非晶質半導体との間で異種物質界面を形成するが、前述
したように、分子ネットワークが連続的に繋がり易くな
るとともにバンドプロファイルがスムーズにつながり易
くなるので、光電変換効率の向上が図れる。また、この
ように結晶系半導体として多結晶シリコン膜を用いる場
合の真性非晶質半導体膜の許容膜厚上限は、結晶系シリ
コン膜についての許容膜厚上限よりも高くなる。In this embodiment, a single crystal semiconductor is exemplified as the crystalline semiconductor. However, the present invention is not limited to this, and a polycrystalline semiconductor may be used. In this case as well, a heterogeneous substance interface is formed with the intrinsic amorphous semiconductor. However, as described above, since the molecular network is easily connected continuously and the band profile is easily connected, the photoelectric conversion efficiency is improved. Can be improved. Further, when the polycrystalline silicon film is used as the crystalline semiconductor, the upper limit of the allowable thickness of the intrinsic amorphous semiconductor film is higher than the upper limit of the allowable thickness of the crystalline silicon film.
【００３１】更に、ドープ膜である非晶質半導体と結晶
系半導体とは互いに逆導電型の関係を有すればよいもの
であり、本実施例とは逆に、結晶系半導体をｐ型とし、
非晶質半導体をｎ型とするようにしてもよい。Further, the amorphous semiconductor and the crystalline semiconductor, which are doped films, only need to have a relationship of opposite conductivity types to each other. Contrary to the present embodiment, the crystalline semiconductor is a p-type semiconductor.
The amorphous semiconductor may be n-type.
【００３２】[0032]
【発明の効果】以上のように、本発明によれば、真性非
晶質半導体はシリコン・ゲルマニウムからなるため、分
子ネットワークは「粗」となり、ネットワークの自由度
（柔軟性）が大きくなるため、異種物質界面での歪みが
減少し、分子ネットワークは連続的に繋がり易くなる。
これにより、界面準位密度が低減される。加えて、上記
非晶質半導体の裏面側でのバンドギャップＥg が結晶系
半導体のＥg に近づくため、光電変換効率が向上する。
一方、光入射側のＥg ＞裏面側のＥg 、の関係が生じて
いるので、当該真性非晶質半導体に水素が均一に含まれ
ている場合と比較して高い電圧を得ることが可能とな
る。As described above, according to the present invention, since the intrinsic amorphous semiconductor is made of silicon-germanium, the molecular network becomes "coarse" and the degree of freedom (flexibility) of the network increases. The strain at the heterogeneous material interface is reduced, and the molecular network is easily connected continuously.
Thereby, the interface state density is reduced. In addition, since the band gap E g on the back surface side of the amorphous semiconductor approaches the E g of the crystalline semiconductor, the photoelectric conversion efficiency is improved.
On the other hand, since the relationship of E g on the light incident side> E g on the back side occurs, a higher voltage can be obtained as compared with the case where hydrogen is uniformly contained in the intrinsic amorphous semiconductor. Becomes
【図１】同図（ａ）は本発明の光起電力装置のバンドプ
ロファイルを示したグラフであり、同図（ｂ）は断面構
造図である。FIG. 1A is a graph showing a band profile of a photovoltaic device of the present invention, and FIG. 1B is a sectional structural view.
【図２】本発明の真性非晶質半導体膜の成膜するとき
の、経過時間に対する各供給ガスの流量変化を示すグラ
フである。FIG. 2 is a graph showing a change in flow rate of each supply gas with respect to elapsed time when an intrinsic amorphous semiconductor film of the present invention is formed.
【図３】本発明の真性非晶質半導体膜成膜開始時のＧｅ
Ｈ4 ／ＳｉＨ4 流量比を異ならせ、その各々の条件下で
得られた真性非晶質半導体膜を用いた光起電力装置の変
換効率を示したグラフである。FIG. 3 shows Ge at the start of forming an intrinsic amorphous semiconductor film of the present invention.
4 is a graph showing the conversion efficiency of a photovoltaic device using an intrinsic amorphous semiconductor film obtained under different conditions of the H 4 / SiH 4 flow rate ratio.
【図４】本発明の光起電力装置と従来のＨＩＴ構造を有
する光起電力装置とにおける、各々の真性非晶質半導体
の膜厚を変化させたときの光電変換効率の変化を示した
グラフである。FIG. 4 is a graph showing changes in photoelectric conversion efficiency of the photovoltaic device of the present invention and a conventional photovoltaic device having a HIT structure when the thickness of each intrinsic amorphous semiconductor is changed. It is.
【図５】従来のｐｎヘテロ接合を有する光起電力装置の
断面構造およびバンドプロファイルを示す模式図であ
る。FIG. 5 is a schematic diagram showing a cross-sectional structure and a band profile of a conventional photovoltaic device having a pn heterojunction.
【図６】従来のＨＩＴ構造を有する光起電力装置の断面
構造およびバンドプロファイルを示す模式図である。FIG. 6 is a schematic view showing a cross-sectional structure and a band profile of a conventional photovoltaic device having a HIT structure.
１ ｎ型単結晶シリコン膜 ２ 真性非晶質半導体膜 ３ ｐ型非晶質シリコン膜 ４ 電極 ５ 透明電極膜 Reference Signs List 1 n-type single-crystal silicon film 2 intrinsic amorphous semiconductor film 3 p-type amorphous silicon film 4 electrode 5 transparent electrode film
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平４−291967（ＪＰ，Ａ) 特開 昭62−111477（ＪＰ，Ａ) 特開 昭59−32181（ＪＰ，Ａ) 特開 昭55−11329（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 31/04 - 31/078 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-4-291967 (JP, A) JP-A-62-111477 (JP, A) JP-A-59-32181 (JP, A) JP-A-55-32181 11329 (JP, A) (58) Field surveyed (Int. Cl. 7 , DB name) H01L 31/04-31/078
Claims (1)
導体と結晶系半導体との間に薄膜の真性非晶質半導体を
介在させた光起電力装置において、前記の真性非晶質半
導体は、シリコン・ゲルマニウムからなり、前記の非晶
質半導体との界面側では結晶系半導体との界面側におけ
るよりもゲルマニウム含有量が少なくされていることを
特徴とする光起電力装置。1. A photovoltaic device in which a thin-film intrinsic amorphous semiconductor is interposed between an amorphous semiconductor and a crystalline semiconductor having a relationship of opposite conductivity type to each other, wherein said intrinsic amorphous semiconductor is A photovoltaic device comprising silicon and germanium, wherein the germanium content is smaller at the interface side with the amorphous semiconductor than at the interface side with the crystalline semiconductor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10500293A JP3197674B2 (en) | 1993-04-06 | 1993-04-06 | Photovoltaic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10500293A JP3197674B2 (en) | 1993-04-06 | 1993-04-06 | Photovoltaic device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06291343A JPH06291343A (en) | 1994-10-18 |
| JP3197674B2 true JP3197674B2 (en) | 2001-08-13 |
Family
ID=14395881
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10500293A Expired - Lifetime JP3197674B2 (en) | 1993-04-06 | 1993-04-06 | Photovoltaic device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3197674B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19524459A1 (en) * | 1995-07-07 | 1997-01-09 | Forschungszentrum Juelich Gmbh | Solar cell, esp. concentrator solar cell - having crystalline silicon@ layer and adjacent amorphous silicon-contg. layer with means for reducing potential barrier in vicinity of amorphous layer boundary face |
| JP3490964B2 (en) | 2000-09-05 | 2004-01-26 | 三洋電機株式会社 | Photovoltaic device |
| FR2880989B1 (en) * | 2005-01-20 | 2007-03-09 | Commissariat Energie Atomique | SEMICONDUCTOR DEVICE WITH HETEROJUNCTIONS AND INTERDIGITAL STRUCTURE |
-
1993
- 1993-04-06 JP JP10500293A patent/JP3197674B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH06291343A (en) | 1994-10-18 |
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