JPH0685291A - Semiconductor device and its manufacture - Google Patents

Semiconductor device and its manufacture

Info

Publication number
JPH0685291A
JPH0685291A JP4254186A JP25418692A JPH0685291A JP H0685291 A JPH0685291 A JP H0685291A JP 4254186 A JP4254186 A JP 4254186A JP 25418692 A JP25418692 A JP 25418692A JP H0685291 A JPH0685291 A JP H0685291A
Authority
JP
Japan
Prior art keywords
layer
semiconductor layer
semiconductor device
crystal silicon
light
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4254186A
Other languages
Japanese (ja)
Inventor
Hitoshi Nishio
仁 西尾
Yoshinori Yamaguchi
美則 山口
Yoshihisa Owada
善久 太和田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kanegafuchi Chemical Industry Co Ltd
Original Assignee
Kanegafuchi Chemical Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kanegafuchi Chemical Industry Co Ltd filed Critical Kanegafuchi Chemical Industry Co Ltd
Priority to JP4254186A priority Critical patent/JPH0685291A/en
Publication of JPH0685291A publication Critical patent/JPH0685291A/en
Pending legal-status Critical Current

Links

Classifications

    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy

Landscapes

  • Photovoltaic Devices (AREA)

Abstract

PURPOSE:To suppress the light deterioration of photoelectric conversion efficiency for high efficiency and improved stability as a solar cell. CONSTITUTION:In a pin (or nip) type semiconductor device. an i-type semiconductor layer 5 is constituted of a first layer 51 and a second layer 52, the first layer 51 is laid out at a light-reception surface side, at the same time the film- formation speed is made slower than that of the second layer 52 for forming a film. Also, when forming a pin (or nip) type semiconductor device, an i-type semiconductor layer 5 is constituted of the first layer 51 and the second layer 52, the first layer 51 is formed at the light-reception surface side, and at the same time, the film-formation speed is made slower than that of the second layer 52. Since the film-formation speed of the first layer 51 is slower than that of the second layer 52, it is desirable that the film thickness of the first layer 51 should be thinner than that of the second layer 52.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体装置の製造法に関
する。さらに詳しくは、光電変換素子用半導体装置の製
造法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device. More specifically, it relates to a method for manufacturing a semiconductor device for photoelectric conversion elements.

【0002】[0002]

【従来の技術】非単結晶の光起電力素子が安定性に欠け
ていることは一般によく知られている。特に非晶質シリ
コンの場合、照射光により伝導度が低下し150℃程度
の熱処理により再び伝導度が回復するというスティーブ
ラー・ロンスキー( Staebler-Wronski )効果と呼ばれ
る現象がある。そのため、かかる素子を用いて太陽電池
を作成した場合、その光電変換効率(以下、変換効率と
いう)が低下する。
2. Description of the Related Art It is generally well known that non-single-crystal photovoltaic devices lack stability. Particularly in the case of amorphous silicon, there is a phenomenon called the Steebler-Wronski effect in which the conductivity is lowered by irradiation light and the conductivity is restored again by a heat treatment at about 150 ° C. Therefore, when a solar cell is created using such an element, its photoelectric conversion efficiency (hereinafter referred to as conversion efficiency) is reduced.

【0003】したがって、比較的安定な光起電力素子を
得るために、i型半導体層を薄膜化し活性層にかかる電
界強度を強め、それにより輸送能を上げるように構成さ
れた光起電力素子が提案されている。
Therefore, in order to obtain a relatively stable photovoltaic element, a photovoltaic element constructed so that the i-type semiconductor layer is thinned to increase the electric field strength applied to the active layer and thereby enhance the transporting ability. Proposed.

【0004】図2はかかる非晶質シリコンを光起電力素
子として用いた太陽電池の概略図である。図において、
1はガラス基板、2透明電極、3はp型半導体層、4は
バッファー層、5はi型半導体層、6はn型半導体層、
7は裏面電極を示す。図2に示す例においては、受光面
側に水素化アモルファスシリコン(a−SiC:H)の
ような広バンドギャップ半導体層が用いられている。こ
のバッファー層4は、図示のごとく、p型半導体層3と
i型半導体層5の界面に設けられており、そしてその不
純物濃度はi型半導体層5にむかって減少させられてい
る。また、ここにおけるi型半導体層5の成膜は、成膜
速度0.2nm/秒でなされている。
FIG. 2 is a schematic view of a solar cell using such amorphous silicon as a photovoltaic element. In the figure,
1 is a glass substrate, 2 transparent electrodes, 3 is a p-type semiconductor layer, 4 is a buffer layer, 5 is an i-type semiconductor layer, 6 is an n-type semiconductor layer,
Reference numeral 7 indicates a back surface electrode. In the example shown in FIG. 2, a wide bandgap semiconductor layer such as hydrogenated amorphous silicon (a-SiC: H) is used on the light-receiving surface side. The buffer layer 4 is provided at the interface between the p-type semiconductor layer 3 and the i-type semiconductor layer 5 as shown in the drawing, and the impurity concentration thereof is reduced toward the i-type semiconductor layer 5. The film formation of the i-type semiconductor layer 5 here is performed at a film formation rate of 0.2 nm / sec.

【0005】しかして、図2に示す太陽電池を実際に作
製し劣化促進試験を実施したところ、i型半導体層5の
膜厚が500nmのもので30%程度の変換効率の低下
が認められ、i型半導体層5の膜厚が100nmのもの
で20%程度の変換効率の低下が認められた。
However, when the solar cell shown in FIG. 2 was actually manufactured and a deterioration acceleration test was carried out, when the film thickness of the i-type semiconductor layer 5 was 500 nm, a decrease in conversion efficiency of about 30% was recognized. When the film thickness of the i-type semiconductor layer 5 was 100 nm, a decrease in conversion efficiency of about 20% was recognized.

【0006】[0006]

【発明が解決しようとする課題】本発明は前記問題点に
鑑みなされたものであって、変換効率の光劣化が抑制さ
れ、高効率で安定性に優れていることにより太陽電池に
好適に用いることができる半導体装置およびその製造法
を提供することを目的とする。
SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and is suitable for use in a solar cell because it suppresses photodegradation of conversion efficiency, has high efficiency, and is excellent in stability. An object of the present invention is to provide a semiconductor device that can be manufactured and a manufacturing method thereof.

【0007】[0007]

【課題を解決するための手段】本発明の半導体装置は、
光起電力素子用半導体装置であって、前記半導体が、少
なくともp型非単結晶シリコン系半導体層、i型非単結
晶シリコン系半導体層およびn型非単結晶シリコン系半
導体層を有し、前記i型非単結晶シリコン系半導体層
が、少なくとも受光面側に用いられる半導体層側に形成
されている第1層と、該第1層に隣接して形成されてい
る第2層とからなり、前記第1層が前記第2層の成膜速
度よりも遅い成膜速度により成膜されてなることを特徴
とする。
The semiconductor device of the present invention comprises:
A semiconductor device for a photovoltaic element, wherein the semiconductor has at least a p-type non-single-crystal silicon-based semiconductor layer, an i-type non-single-crystal silicon-based semiconductor layer, and an n-type non-single-crystal silicon-based semiconductor layer, The i-type non-single-crystal silicon-based semiconductor layer comprises at least a first layer formed on the semiconductor layer side used on the light-receiving surface side and a second layer formed adjacent to the first layer, It is characterized in that the first layer is formed at a film formation rate lower than the film formation rate of the second layer.

【0008】本発明の半導体装置においては、前記受光
面側に用いられる半導体層がp型非単結晶シリコン系半
導体層またはn型非単結晶シリコン系半導体層であるの
が好ましい。
In the semiconductor device of the present invention, it is preferable that the semiconductor layer used on the light receiving surface side is a p-type non-single crystal silicon semiconductor layer or an n-type non-single crystal silicon semiconductor layer.

【0009】また、本発明の半導体装置においては、前
記第1層の膜厚が10nm以上30nm以下であり、前
記第1層の成膜速度が0.03nm/秒以上0.1nm
/秒以下であるのが好ましい。
Further, in the semiconductor device of the present invention, the film thickness of the first layer is 10 nm or more and 30 nm or less, and the film formation rate of the first layer is 0.03 nm / sec or more and 0.1 nm or more.
/ Sec or less is preferable.

【0010】さらに、本発明の半導体装置においては、
前記受光面側に用いられる半導体層が水素化アモルファ
スシリコンからなるのが好ましい。
Further, in the semiconductor device of the present invention,
It is preferable that the semiconductor layer used on the light receiving surface side is made of hydrogenated amorphous silicon.

【0011】本発明の製造法は、光起電力素子用半導体
装置の製造法であって、前記半導体が、少なくともp型
非単結晶シリコン系半導体層、i型非単結晶シリコン系
半導体層およびn型非単結晶シリコン系半導体層を有
し、前記i型非単結晶シリコン系半導体層が、少なくと
も受光面側に用いられる半導体層側に形成されている第
1層と、該第1層に隣接して形成されている第2層とか
らなり、前記第1層の成膜速度が、前記第2層の成膜速
度よりも遅いことを特徴とする。
The manufacturing method of the present invention is a method for manufacturing a semiconductor device for a photovoltaic element, wherein the semiconductor is at least a p-type non-single-crystal silicon-based semiconductor layer, an i-type non-single-crystal silicon-based semiconductor layer, and an n-type. Type non-single-crystal silicon-based semiconductor layer, the i-type non-single-crystal silicon-based semiconductor layer is adjacent to the first layer formed on at least the semiconductor layer side used on the light-receiving surface side. And a second layer formed as described above, and the film forming rate of the first layer is slower than the film forming rate of the second layer.

【0012】本発明の製造法においては、前記受光面側
に用いられる半導体層がp型またはn型非単結晶シリコ
ン系半導体層であるのが好ましい。
In the manufacturing method of the present invention, it is preferable that the semiconductor layer used on the light-receiving surface side is a p-type or n-type non-single-crystal silicon semiconductor layer.

【0013】また、本発明の製造法においては、前記第
1層の膜厚が10nm以上30nm以下であり、前記第
1層の成膜速度が0.03nm/秒以上0.1nm/秒
以下であるのが好ましい。
In the manufacturing method of the present invention, the film thickness of the first layer is 10 nm or more and 30 nm or less, and the film forming rate of the first layer is 0.03 nm / sec or more and 0.1 nm / sec or less. Preferably.

【0014】さらに、本発明の製造法においては、前記
受光面側に用いられる半導体層が水素化アモルファスシ
リコンからなるのが好ましい。
Further, in the manufacturing method of the present invention, it is preferable that the semiconductor layer used on the light-receiving surface side is made of hydrogenated amorphous silicon.

【0015】[0015]

【作用】本発明の半導体装置においては、前記のごと
く、i型半導体層が少なくとも受光面側の第1層とこれ
に隣接する第2層とからな、しかも第1層の成膜速度が
第2層のそれよりも遅くされているので、受光面側のp
/i(nip型の場合はn/i)界面付近の膜質が安定
に保たれる。そのため、本発明の半導体装置は光劣化が
抑制され高効率で安定性に優れている。また、本発明の
製造法によれば、かかる特性を有する半導体装置を作製
することができる。
In the semiconductor device of the present invention, as described above, the i-type semiconductor layer is composed of at least the first layer on the light-receiving surface side and the second layer adjacent thereto, and the first layer has a first film formation rate. Since it is slower than that of the two layers, p on the light-receiving surface side
The film quality near the / i (n / i in the case of nip type) interface is stably maintained. Therefore, the semiconductor device of the present invention is suppressed from photodegradation and is highly efficient and excellent in stability. Moreover, according to the manufacturing method of the present invention, a semiconductor device having such characteristics can be manufactured.

【0016】[0016]

【実施例】以下、添付図面を参照しながら本発明を実施
例に基づいて説明するが、本発明はかかる実施例のみに
限定されるものではない。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described based on embodiments with reference to the accompanying drawings, but the present invention is not limited to such embodiments.

【0017】図1は本発明の半導体装置を用いた太陽電
池の概略図である。図において、1は透光性基板、2は
透明電極、3はp型非単結晶シリコン系半導体層、4は
バッファー層、5はi型非単結晶シリコン系半導体層、
6は微結晶化n型非単結晶シリコン系半導体層、7は裏
面電極を示す。
FIG. 1 is a schematic view of a solar cell using the semiconductor device of the present invention. In the figure, 1 is a transparent substrate, 2 is a transparent electrode, 3 is a p-type non-single-crystal silicon-based semiconductor layer, 4 is a buffer layer, 5 is an i-type non-single-crystal silicon-based semiconductor layer,
Reference numeral 6 indicates a microcrystallized n-type non-single-crystal silicon semiconductor layer, and 7 indicates a back surface electrode.

【0018】本発明における非単結晶シリコン系半導体
としては、例えば、Si、SiC、SiN、SiGe、
SiSn等の水素化合金、フッ素化合金等の一般に光起
電力素子に使用されるアモルファス系、微結晶を含むア
モルファス系または多結晶系の半導体があげられる。
Examples of the non-single-crystal silicon semiconductor in the present invention include Si, SiC, SiN, SiGe,
Examples include hydrogenated alloys such as SiSn, fluorinated alloys, and other amorphous semiconductors generally used in photovoltaic devices, and amorphous or polycrystalline semiconductors including microcrystals.

【0019】非単結晶シリコン系半導体は、窓層材料と
して広バンドギャップ半導体が用いられ、pin型ある
いはnip型の光起電力素子とされる。光起電力素子を
形成する各非単結晶シリコン系半導体の厚さは特に限定
されず、通常光起電力素子に使用される範囲であればよ
い。
A wide bandgap semiconductor is used as the window layer material for the non-single crystal silicon semiconductor, and is a pin-type or nip-type photovoltaic element. The thickness of each non-single-crystal silicon-based semiconductor forming the photovoltaic element is not particularly limited and may be in the range normally used for photovoltaic elements.

【0020】本発明においては、受光面側のp型半導体
層3(nip型の場合はn型半導体層6)側にi型半導
体層を成膜する場合の初期膜(第1層)形成時の成膜速
度を遅くし、初期膜(第1層)形成後の第2層の成膜速
度を早くしている。成膜速度の調整方法としては、RF
パワーを増減させる方法、圧力を増減させる方法、成膜
温度を増減させる方法、希釈水素量を増減させる方法な
どがあげられる。また、これらの方法を組み合わせるこ
とも可能である。
In the present invention, when the initial film (first layer) is formed when the i-type semiconductor layer is formed on the p-type semiconductor layer 3 (n-type semiconductor layer 6 in the case of nip type) side on the light-receiving surface side. The film forming speed of (2) is slowed down, and the film forming speed of the second layer after the initial film (first layer) is formed is increased. As a method of adjusting the film forming speed, RF is used.
Examples include a method of increasing / decreasing the power, a method of increasing / decreasing the pressure, a method of increasing / decreasing the film forming temperature, and a method of increasing / decreasing the amount of diluted hydrogen. It is also possible to combine these methods.

【0021】初期膜(第1層)の膜厚は、成膜速度が遅
いためできるだけ薄い方がよいが、p/i(nip型の
場合はn/i、以下、同様)界面の安定性を保つために
は10nm以上の膜厚が好ましい。ただし、30nmを
超えないのが望ましい。
The film thickness of the initial film (first layer) is preferably as thin as possible because the film forming speed is slow, but the stability of the p / i (n / i in the case of nip type, the same applies below) interface is maintained. In order to keep it, a film thickness of 10 nm or more is preferable. However, it is desirable not to exceed 30 nm.

【0022】初期膜(第1層)の成膜速度は、p/i界
面の安定性を考えた場合できるだけ遅い方がよいが、製
造装置の操作性を考慮すれば、成膜速度を最小で0.0
3nm/秒とするのが好ましい。一方、成膜速度が早す
ぎるとp/i界面が荒されるので、最大0.1nm/秒
におさえる必要がある。
The film formation rate of the initial film (first layer) should be as slow as possible in consideration of the stability of the p / i interface, but if the operability of the manufacturing apparatus is taken into consideration, the film formation rate should be minimized. 0.0
It is preferably 3 nm / sec. On the other hand, if the film formation rate is too fast, the p / i interface is roughened, so it is necessary to keep the maximum at 0.1 nm / sec.

【0023】受光面側の窓層(図1に示す実施例におい
ては、p型半導体層3が相当する)としては、広バンド
ギャップのSiC、SiNなどが、ドーピング特性から
考えて望ましい。本実施例では透明電極2としてSnO
2 を使用しているが、ITO、ZnO等あるいはこれら
の複層膜でもよい。
As the window layer on the light-receiving surface side (corresponding to the p-type semiconductor layer 3 in the embodiment shown in FIG. 1), wide bandgap SiC, SiN or the like is preferable in view of the doping characteristics. In this embodiment, SnO is used as the transparent electrode 2.
Although 2 is used, ITO, ZnO or the like or a multilayer film of these may be used.

【0024】なお、p型半導体層3およびn型半導体層
6のその余の構成ならびに透光性基板1、バッファー層
4、裏面電極8の構成は、従来の太陽電池と同様である
ので、その構成の詳細な説明は省略する。
Since the remaining structure of the p-type semiconductor layer 3 and the n-type semiconductor layer 6 and the structures of the transparent substrate 1, the buffer layer 4 and the back electrode 8 are the same as those of the conventional solar cell, Detailed description of the configuration is omitted.

【0025】以下、本発明の半導体装置の製造法を具体
的な実施例に基づいて説明する。
The method for manufacturing the semiconductor device of the present invention will be described below based on specific examples.

【0026】実施例および比較例 平行平板容量結合型グロー放電装置を用いて、半導体各
層を成膜形成し有効面積1.0cm2 の太陽電池を作製
した。なお、成膜は下記により行った。SnO2 透明電
極2が成膜されたガラス基板1上に、膜厚25nmのp
型半導体層3をガス流量SiH4 (50sccm)、C
4 (35sccm)、B2 6 (1000ppmH2
希釈品)(100sccm)、H2 (500sccm)
にて、反応圧力1.0Torr、ヒーター温度200
℃、RFパワー50mW/cm2 で成膜した。つぎに膜
厚10nmのバッファー層4をガス流量SiH4 (50
sccm)、CH4 (35sccm)、H2 (500s
ccm)にて、反応圧力1.0Torr、ヒーター温度
200℃、RFパワー50mW/cm2 で成膜した。し
かるのち、膜厚30nmのi型半導体層(第1層)51
をガス流量SiH4 (50sccm)にて、反応圧力
0.3Torr、ヒーター温度200℃、RFパワー3
0mW/cm2 で成膜し、引続き膜厚400nmのi型
半導体層(第2層)52をガス流量SiH4 (50sc
cm)にて、反応圧力0.3Torr、ヒーター温度2
00℃、RFパワー50mW/cm2 として成膜速度を
上げて成膜し、i型半導体層5形成した。つぎに膜厚3
00Åの微結晶化n型半導体層6をガス流量SiH
4 (5sccm)、PH3 (1000ppmH2 希釈
品)(100sccm)、H2 (200sccm)に
て、反応圧力1.0Torr、ヒーター温度200℃、
RFパワー500mW/cm2 で成膜した。さらに裏面
電極7を作製し、太陽電池を完成させた(実施例)。
Examples and Comparative Examples Using a parallel plate capacitively coupled glow discharge device, each semiconductor layer was formed and formed into a solar cell having an effective area of 1.0 cm 2 . The film formation was performed as follows. On the glass substrate 1 on which the SnO 2 transparent electrode 2 is formed, a p film having a thickness of 25 nm is formed.
The gas flow rate of SiH 4 (50 sccm), C
H 4 (35 sccm), B 2 H 6 (1000 ppm H 2
Diluted product) (100sccm), H 2 (500sccm)
At a reaction pressure of 1.0 Torr and a heater temperature of 200
A film was formed at a temperature of 50 ° C. and RF power of 50 mW / cm 2 . Next, the buffer layer 4 having a film thickness of 10 nm is subjected to a gas flow rate SiH 4 (50
sccm), CH 4 (35 sccm), H 2 (500s
ccm), the reaction pressure was 1.0 Torr, the heater temperature was 200 ° C., and the RF power was 50 mW / cm 2 . Then, the i-type semiconductor layer (first layer) 51 having a film thickness of 30 nm is formed.
At a gas flow rate of SiH 4 (50 sccm), reaction pressure of 0.3 Torr, heater temperature of 200 ° C., RF power of 3
The i-type semiconductor layer (second layer) 52 having a film thickness of 400 nm is continuously formed at 0 mW / cm 2 , and the gas flow rate is SiH 4 (50 sc).
cm), reaction pressure 0.3 Torr, heater temperature 2
The i-type semiconductor layer 5 was formed by increasing the film formation rate at 00 ° C. and RF power of 50 mW / cm 2 . Next, the film thickness 3
The gas flow rate SiH is applied to the microcrystallized n-type semiconductor layer 6 of 00Å
4 (5sccm), PH 3 ( 1000ppmH 2 diluted mixture) (100 sccm), with H 2 (200sccm), reaction pressure 1.0 Torr, a heater temperature of 200 ° C.,
A film was formed with an RF power of 500 mW / cm 2 . Furthermore, the back surface electrode 7 was produced, and the solar cell was completed (Example).

【0027】比較として従来の製法により太陽電池を作
製した(比較例)。
For comparison, a solar cell was manufactured by a conventional manufacturing method (comparative example).

【0028】得られた実施例および比較例の太陽電池に
ついて、48℃の温度条件下、AM1.5 100mW
/cm2の疑似太陽光により500時間の劣化促進試験
を行った。その結果、比較例の太陽電池においては、1
8〜20%の効率低下が観測されたのに対し、実施例の
太陽電池においては、10〜15%の効率低下しか認め
られなかった。
Regarding the obtained solar cells of Examples and Comparative Examples, AM1.5 100 mW under a temperature condition of 48 ° C.
A deterioration acceleration test was carried out for 500 hours by using artificial sunlight of / cm 2 . As a result, in the solar cell of the comparative example, 1
While a decrease in efficiency of 8 to 20% was observed, only a decrease in efficiency of 10 to 15% was observed in the solar cells of the examples.

【0029】[0029]

【発明の効果】以上説明したように、本発明の半導体装
置においては、受光面側のp型半導体層あるいはn型半
導体層側にi型半導体層を成膜する場合、第1層の成膜
速度を第2層のそれよりも遅くして、p/iまたはn/
i界面での安定性を保っているので、光劣化が抑制さ
れ、高効率で安定性に優れている。そのため、太陽電池
に好適に用いることができる。
As described above, in the semiconductor device of the present invention, when the i-type semiconductor layer is formed on the light-receiving surface side of the p-type semiconductor layer or the n-type semiconductor layer side, the first layer is formed. The speed is slower than that of the second layer, and p / i or n /
Since the stability at the i interface is maintained, photodegradation is suppressed, high efficiency and excellent stability are achieved. Therefore, it can be suitably used for a solar cell.

【0030】また、本発明の製造法によれば、かかる特
性を有する半導体装置を作製することができる。
According to the manufacturing method of the present invention, a semiconductor device having such characteristics can be manufactured.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の製造法により作製した半導体装置を用
いた太陽電池の一実施例の概略図である。
FIG. 1 is a schematic view of an example of a solar cell using a semiconductor device manufactured by the manufacturing method of the present invention.

【図2】従来の太陽電池の概略図である。FIG. 2 is a schematic view of a conventional solar cell.

【符号の説明】[Explanation of symbols]

1 透光性基板(ガラス基板) 2 透明電極 3 p型非単結晶シリコン半導体層(p型半導体層) 4 バッファー層 5 i型非単結晶シリコン半導体層(i型半導体層) 51 第1層(初期層) 52 第2層 6 微結晶化n型非単結晶シリコン半導体層(n型半
導体層) 7 裏面電極
1 translucent substrate (glass substrate) 2 transparent electrode 3 p-type non-single-crystal silicon semiconductor layer (p-type semiconductor layer) 4 buffer layer 5 i-type non-single-crystal silicon semiconductor layer (i-type semiconductor layer) 51 first layer ( Initial layer) 52 Second layer 6 Microcrystallized n-type non-single-crystal silicon semiconductor layer (n-type semiconductor layer) 7 Back electrode

【手続補正書】[Procedure amendment]

【提出日】平成5年3月12日[Submission date] March 12, 1993

【手続補正1】[Procedure Amendment 1]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】特許請求の範囲[Name of item to be amended] Claims

【補正方法】変更[Correction method] Change

【補正内容】[Correction content]

【特許請求の範囲】[Claims]

Claims (1)

【特許請求の範囲】 【請求項1】 光起電力素子用半導体装置であって、 前記半導体が、少なくともp型非単結晶シリコン系半導
体層、i型非単結晶シリコン系半導体層およびn型非単
結晶シリコン系半導体層を有し、 前記i型非単結晶シリコン系半導体層が、少なくとも受
光面側に用いられる半導体層側に形成されている第1層
と、該第1層に隣接して形成されている第2層とからな
り、 前記第1層が前記第2層の成膜速度よりも遅い成膜速度
により成膜されてなることを特徴とする半導体装置。 【請求2項】 前記受光面側に用いられる半導体層がp
型非単結晶シリコン系半導体層であることを特徴とする
請求項1記載の半導体装置。 【請求3項】 前記受光面側に用いられる半導体層がn
型非単結晶シリコン系半導体層であることを特徴とする
請求項1記載の半導体装置。 【請求項4】 前記第1層の膜厚が、10nm以上30
nm以下であることを特徴とする請求項1、2または3
記載の半導体装置。 【請求項5】 前記第1層の成膜速度が、0.03nm
/秒以上0.1nm/秒以下であることを特徴とする請
求項1、2または3記載の半導体装置。 【請求項6】 前記受光面側に用いられる半導体層が水
素化アモルファスシリコンからなることを特徴とする請
求項1、2または3記載の半導体装置。 【請求項7】 光起電力素子用半導体装置の製造法であ
って、 前記半導体が、少なくともp型非単結晶シリコン系半導
体層、i型非単結晶シリコン系半導体層およびn型非単
結晶シリコン系半導体層を有し、 前記i型非単結晶シリコン系半導体層が、少なくとも受
光面側に用いられる半導体層側に形成されている第1層
と、該第1層に隣接して形成されている第2層とからな
り、 前記第1層の成膜速度が、前記第2層の成膜速度よりも
遅いことを特徴とする半導体装置の製造法。 【請求8項】 前記受光面側に用いられる半導体層がp
型非単結晶シリコン系半導体層であることを特徴とする
請求項7記載の半導体装置の製造法。 【請求9項】 前記受光面側に用いられる半導体層がn
型非単結晶シリコン系半導体層であることを特徴とする
請求項7記載の半導体装置の製造法。 【請求項10】 前記第1層の膜厚が、10nm以上3
0nm以下であることを特徴とする請求項7、8または
9記載の半導体装置の製造法。 【請求項11】 前記第1層の成膜速度が、0.03n
m/秒以上0.1nm/秒以下であることを特徴とする
請求項7、8または9記載の半導体装置の製造法。 【請求項12】 前記受光面側に用いられる半導体層が
水素化アモルファスシリコンからなることを特徴とする
請求項7、8または9記載の半導体装置の製造方法。
1. A semiconductor device for a photovoltaic element, wherein the semiconductor is at least a p-type non-single-crystal silicon semiconductor layer, an i-type non-single-crystal silicon semiconductor layer, and an n-type non-single crystal silicon semiconductor layer. A single crystal silicon-based semiconductor layer, wherein the i-type non-single crystal silicon-based semiconductor layer is adjacent to the first layer formed on at least the semiconductor layer side used on the light-receiving surface side; A semiconductor device comprising a formed second layer, wherein the first layer is formed at a film formation rate slower than a film formation rate of the second layer. 2. The semiconductor layer used on the light-receiving surface side is p
The semiconductor device according to claim 1, wherein the semiconductor device is a non-single-crystal silicon semiconductor layer. 3. The semiconductor layer used on the light-receiving surface side is n
The semiconductor device according to claim 1, wherein the semiconductor device is a non-single-crystal silicon semiconductor layer. 4. The film thickness of the first layer is 10 nm or more and 30.
nm or less, Claim 1, 2 or 3 characterized by the above-mentioned.
The semiconductor device described. 5. The film forming rate of the first layer is 0.03 nm.
/ Second or more and 0.1 nm / second or less, The semiconductor device according to claim 1, 2 or 3. 6. The semiconductor device according to claim 1, wherein the semiconductor layer used on the light-receiving surface side is made of hydrogenated amorphous silicon. 7. A method for manufacturing a semiconductor device for a photovoltaic element, wherein the semiconductor is at least a p-type non-single crystal silicon semiconductor layer, an i-type non-single crystal silicon semiconductor layer and an n-type non-single crystal silicon. A semiconductor layer, and the i-type non-single-crystal silicon semiconductor layer is formed adjacent to the first layer formed at least on the semiconductor layer side used on the light-receiving surface side. A second layer which is present, wherein the film forming rate of the first layer is slower than the film forming rate of the second layer. 8. The semiconductor layer used on the light receiving surface side is p
8. The method of manufacturing a semiconductor device according to claim 7, wherein the semiconductor device is a non-single crystal silicon semiconductor layer. 9. The semiconductor layer used on the light-receiving surface side is n
8. The method of manufacturing a semiconductor device according to claim 7, wherein the semiconductor device is a non-single crystal silicon semiconductor layer. 10. The film thickness of the first layer is 10 nm or more and 3
The method for manufacturing a semiconductor device according to claim 7, 8 or 9, wherein the thickness is 0 nm or less. 11. The deposition rate of the first layer is 0.03 n
The method for manufacturing a semiconductor device according to claim 7, 8 or 9, wherein the value is m / sec or more and 0.1 nm / sec or less. 12. The method of manufacturing a semiconductor device according to claim 7, wherein the semiconductor layer used on the light-receiving surface side is made of hydrogenated amorphous silicon.
JP4254186A 1992-08-28 1992-08-28 Semiconductor device and its manufacture Pending JPH0685291A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4254186A JPH0685291A (en) 1992-08-28 1992-08-28 Semiconductor device and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4254186A JPH0685291A (en) 1992-08-28 1992-08-28 Semiconductor device and its manufacture

Publications (1)

Publication Number Publication Date
JPH0685291A true JPH0685291A (en) 1994-03-25

Family

ID=17261434

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4254186A Pending JPH0685291A (en) 1992-08-28 1992-08-28 Semiconductor device and its manufacture

Country Status (1)

Country Link
JP (1) JPH0685291A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6531654B2 (en) 2000-05-23 2003-03-11 Canon Kabushiki Kaisha Semiconductor thin-film formation process, and amorphous silicon solar-cell device
US7534628B2 (en) 2006-10-12 2009-05-19 Canon Kabushiki Kaisha Method for forming semiconductor device and method for forming photovoltaic device
KR101528455B1 (en) * 2009-01-12 2015-06-10 주성엔지니어링(주) Thin film type Solar Cell and Method for manufacturing the same
KR20210040677A (en) * 2019-10-04 2021-04-14 한국재료연구원 Semitransparent thin film solar cell and manufacturing method of the same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6531654B2 (en) 2000-05-23 2003-03-11 Canon Kabushiki Kaisha Semiconductor thin-film formation process, and amorphous silicon solar-cell device
US7534628B2 (en) 2006-10-12 2009-05-19 Canon Kabushiki Kaisha Method for forming semiconductor device and method for forming photovoltaic device
KR101528455B1 (en) * 2009-01-12 2015-06-10 주성엔지니어링(주) Thin film type Solar Cell and Method for manufacturing the same
KR20210040677A (en) * 2019-10-04 2021-04-14 한국재료연구원 Semitransparent thin film solar cell and manufacturing method of the same

Similar Documents

Publication Publication Date Title
US6368892B1 (en) Monolithic multi-junction solar cells with amorphous silicon and CIS and their alloys
US7030413B2 (en) Photovoltaic device with intrinsic amorphous film at junction, having varied optical band gap through thickness thereof
JP2740284B2 (en) Photovoltaic element
JPS6249672A (en) Amorphous photovoltaic element
JP2009503848A (en) Composition gradient photovoltaic device, manufacturing method and related products
JP4284582B2 (en) Multi-junction thin film solar cell and manufacturing method thereof
EP0099720B1 (en) Photovoltaic device
JPH04130671A (en) Photovoltaic device
JP2004260014A (en) Multilayer type thin film photoelectric converter
JPS62234379A (en) Semiconductor device
JPS6334632B2 (en)
JPH0685291A (en) Semiconductor device and its manufacture
JP4110718B2 (en) Manufacturing method of multi-junction thin film solar cell
JPH11274527A (en) Photovoltaic device
JP2002016271A (en) Thin-film photoelectric conversion element
JPH0282582A (en) Laminated amorphous silicon solar cell
JP2958491B2 (en) Method for manufacturing photoelectric conversion device
JP3197674B2 (en) Photovoltaic device
JP2744680B2 (en) Manufacturing method of thin film solar cell
JP2001284619A (en) Phtovoltaic device
JPH0282655A (en) Manufacture of photovolatic device
JPS6152992B2 (en)
JP4124309B2 (en) Photovoltaic device manufacturing method
JP2545066B2 (en) Semiconductor device
JPS62165374A (en) Amorphous photovoltaic element

Legal Events

Date Code Title Description
A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20011009