JP2545066B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2545066B2 JP2545066B2 JP60255681A JP25568185A JP2545066B2 JP 2545066 B2 JP2545066 B2 JP 2545066B2 JP 60255681 A JP60255681 A JP 60255681A JP 25568185 A JP25568185 A JP 25568185A JP 2545066 B2 JP2545066 B2 JP 2545066B2
- Authority
- JP
- Japan
- Prior art keywords
- dopant
- layer
- type
- type layer
- junction interface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 53
- 239000002019 doping agent Substances 0.000 claims description 46
- 239000000463 material Substances 0.000 claims description 6
- 230000000737 periodic effect Effects 0.000 claims description 6
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- 229910052787 antimony Inorganic materials 0.000 claims description 2
- 229910052785 arsenic Inorganic materials 0.000 claims description 2
- 230000005684 electric field Effects 0.000 claims description 2
- 229910052733 gallium Inorganic materials 0.000 claims description 2
- 229910052738 indium Inorganic materials 0.000 claims description 2
- 239000000203 mixture Substances 0.000 claims description 2
- 229910052757 nitrogen Inorganic materials 0.000 claims description 2
- 229910052716 thallium Inorganic materials 0.000 claims description 2
- 230000007423 decrease Effects 0.000 claims 1
- 239000010410 layer Substances 0.000 description 69
- 229910021417 amorphous silicon Inorganic materials 0.000 description 11
- 238000009826 distribution Methods 0.000 description 11
- 238000004519 manufacturing process Methods 0.000 description 6
- 230000000052 comparative effect Effects 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 229910017817 a-Ge Inorganic materials 0.000 description 2
- 230000004913 activation Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910020328 SiSn Inorganic materials 0.000 description 1
- -1 a-SiC: H Chemical compound 0.000 description 1
- 229910017875 a-SiN Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000009616 inductively coupled plasma Methods 0.000 description 1
- 230000031700 light absorption Effects 0.000 description 1
- 229910021424 microcrystalline silicon Inorganic materials 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910052699 polonium Inorganic materials 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 229910052714 tellurium Inorganic materials 0.000 description 1
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
- H01L31/075—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PIN type, e.g. amorphous silicon PIN solar cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/548—Amorphous silicon PV cells
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Photovoltaic Devices (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関する。The present invention relates to a semiconductor device.
非晶質半導体層を含む太陽電池などの半導体装置の材
料として、ａ−Si:H、ａ−SiC:H、ａ−SiGe:H、ａ−Si
N:H、ａ−Si:F:H、ａ−Ge:Hなどや、これらに微結晶相
を含む半導体が用いられている。As a material of a semiconductor device such as a solar cell including an amorphous semiconductor layer, a-Si: H, a-SiC: H, a-SiGe: H, a-Si
N: H, a-Si: F: H, a-Ge: H, and the like, and semiconductors containing a microcrystalline phase in these are used.
従来の太陽電池は、前記材料をpinあるいはnipの順に
同種の非晶質半導体あるいはドープ層のみ広い禁止帯幅
を有する異種の非晶質半導体を順次堆積した構造であ
り、ｐ型層あるいはｎ型層のドーパントの密度は素子作
製時および作製後の熱拡散による分布を除けば、層の厚
さ方向にわたって一様で、通常0.01〜5atm％である。A conventional solar cell has a structure in which the same type of amorphous semiconductor or a different type of amorphous semiconductor having a wide band gap only in a doped layer is sequentially deposited on the above material in the order of pin or nip. The density of the dopant in the layer is uniform in the thickness direction of the layer and is usually 0.01 to 5 atm%, except for the distribution due to thermal diffusion during and after device fabrication.
しかし、この構造の半導体装置は素子内部の内蔵電界
が弱く、光照射時、とくに低照度光照射時の開放電圧Vo
cが充分に大きくないという問題がある。とくに上記半
導体装置を光起電力素子として乾電池の代替電源に用い
るばあい、直列接続の段数を多くとらなければならず、
素子構成上の問題となっている。However, the semiconductor device with this structure has a weak built-in electric field inside the element, and the open-circuit voltage Vo during light irradiation, especially under low illuminance light irradiation, is low.
There is a problem that c is not large enough. Especially when the above semiconductor device is used as an alternative power source for a dry cell as a photovoltaic element, a large number of stages must be connected in series.
This is a problem in device configuration.
本発明はこのような問題を解決するためになされたも
のである。The present invention has been made to solve such a problem.
本発明の半導体装置は、pin型の非晶質を含む半導体
層と少なくとも２つの電極とを有する半導体装置におい
て、ｐ型層またはｎ型層のドーパントの量がp/電極また
はn/電極接合界面からp/iまたはn/i接合界面に向かって
段階的に減少し当該p/iまたはn/i接合界面で実質的にゼ
ロになるように、p/iまたはn/i接合界面に向かうにした
がいドーパントの導入量を段階的に減少せしめてなる部
分をｐ型層またはｎ型層の少なくとも１つに設けてお
り、前記ｐ型層またはｎ型層のうちドーパント量が段階
的に変化している層が一定組成のａ−SiC:H層であるこ
とを特徴としている。The semiconductor device of the present invention is a semiconductor device having a semiconductor layer containing pin-type amorphous material and at least two electrodes, wherein the amount of dopant in the p-type layer or the n-type layer is the p / electrode or n / electrode junction interface. From the p / i or n / i junction interface to a substantially zero value at the p / i or n / i junction interface. Accordingly, a portion formed by gradually reducing the introduction amount of the dopant is provided in at least one of the p-type layer and the n-type layer, and the dopant amount in the p-type layer or the n-type layer is changed stepwise. It is characterized in that the existing layer is an a-SiC: H layer having a constant composition.
本発明に用いるpin型（nip型）の非晶質を含む半導体
層を構成するｉ型層としては、たとえばａ−Si:H、ａ−
SiGe:H、ａ−Ge:H、ａ−Si:F:H、ａ−SiN:H、ａ−SiSn:
Hなどや、それらにホウ素やリンを微量ドープしたもの
などから形成された厚さ2500〜9000Å程度の層、ｐ型層
としては、たとえばａ−SiC:H、μｃ−Si:H、ａ−Si:H
などにｐ型用ドーパントである周期律表III a族の元素
をドープしたものなどから形成された厚さ80〜300Å程
度の層、ｎ型層としては、たとえばａ−Si:H、μｃ−S
i:H、ａ−SiC:Hなどにｎ型用ドーパントである周期律表
V a族の元素をドープしたものなどから形成された厚さ8
0〜300Å程度の層があげられるが、これらに限定される
ものではない。Examples of the i-type layer forming the semiconductor layer containing a pin-type (nip-type) amorphous material used in the present invention include a-Si: H and a-Si.
SiGe: H, a-Ge: H, a-Si: F: H, a-SiN: H, a-SiSn:
Examples of the p-type layer having a thickness of 2500 to 9000 Å formed from H or the like, or those slightly doped with boron or phosphorus, such as a-SiC: H, μc-Si: H, a-Si : H
A layer having a thickness of about 80 to 300 Å formed by doping an element of Group IIIa of the periodic table, which is a p-type dopant, etc., and an n-type layer is, for example, a-Si: H, μc-S.
Periodic table that is an n-type dopant for i: H, a-SiC: H, etc.
Thickness 8 formed from doped elements of group V a
The layer is, for example, 0 to 300Å, but is not limited thereto.
前記ｐ型層のうちでは、ａ−SiC:HにIII a族の元素を
ドープした層が、活性化エネルギーが小さい、光吸収ロ
スが少ないなどの点から好ましく、また前記ｎ型層のう
ちでは、ａ−SiC:HにV a族の元素をドープした層が、活
性化エネルギーが小さい、導電率が高いなどの点から好
ましい。Among the p-type layers, a layer obtained by doping a-SiC: H with a Group IIIa element is preferable from the viewpoints of low activation energy, low light absorption loss, and the like, and of the n-type layers, , A-SiC: H doped with a V a group element is preferable from the viewpoint of low activation energy and high conductivity.
前記説明ににおいては、ｐ型用ドーパントとして周期
律表III a族の元素、すなわちＢ、Al、Ga、In、Tl、ｎ
型用ドーパントとして周期律表のV a族の元素、すなわ
ちＮ、Ｐ、As、Sb、Te、Poをあげたが、ドーピングする
ことにより半導体をｐ型あるいはｎ型の導電タイプを示
すものにするものであれば、これらに限定されるもので
ない。In the above description, as a p-type dopant, an element of Group IIIa of the periodic table, that is, B, Al, Ga, In, Tl, n.
As the type dopants, elements of the V a group of the periodic table, that is, N, P, As, Sb, Te, and Po have been mentioned. Doping makes the semiconductor exhibit p-type or n-type conductivity type. If it is a thing, it will not be limited to these.
本明細書にいう非晶質を含む半導体層とは、非晶質半
導体、非晶質半導体に微結晶状半導体が微結晶粒状に分
布するもの、大きな結晶粒の結晶半導体の間を非結晶半
導体がうめるように分布するものなどから形成された層
状の半導体のことである。As used herein, a semiconductor layer containing amorphous includes an amorphous semiconductor, an amorphous semiconductor in which microcrystalline semiconductors are distributed in microcrystalline grains, and an amorphous semiconductor between crystal semiconductors having large crystal grains. It is a layered semiconductor formed from such things as a dense distribution.
本発明におけるpin型（nip型）半導体層においては、
ｐ型層またはｎ型層のドーパントの量がp/電極またはn/
電極接合界面からp/iまたはn/i接合界面に向かって段階
的に減少し当該p/iまたはn/i接合界面で実質的にゼロに
なるように、p/iまたはn/i接合界面に向かうにしたがい
ドーパントの導入量を段階的に減少せしめてなる部分が
ｐ型層またはｎ型層の少なくとも１つに設けられてい
る。In the pin type (nip type) semiconductor layer of the present invention,
The amount of dopant in the p-type layer or n-type layer is p / electrode or n /
The p / i or n / i junction interface is gradually reduced from the electrode junction interface toward the p / i or n / i junction interface and becomes substantially zero at the p / i or n / i junction interface. At least one of the p-type layer and the n-type layer is provided with a portion in which the amount of introduction of the dopant is gradually reduced toward the.
第１図は本発明の半導体装置の一実施態様を示す説明
図であり、透明電極（２）を有するガラス基板（１）上
に、p/i接合界面でのドーパントの量が最も少なくなる
ようにｐ型半導体層（３）が設けられ、その上にｉ型半
導体層（４）、ついでｎ型半導体層（５）が設けられ、
さらに裏面電極（６）が設けられていることを示す図で
ある。FIG. 1 is an explanatory view showing one embodiment of the semiconductor device of the present invention, in which the amount of dopant at the p / i junction interface is minimized on the glass substrate (1) having the transparent electrode (2). Is provided with a p-type semiconductor layer (3), and an i-type semiconductor layer (4) and then an n-type semiconductor layer (5) are provided thereon,
It is a figure which shows that the back surface electrode (6) is further provided.
第１図の半導体装置では、p/i接合界面でのドーパン
トの量が最も少なくなるようにされているが、ｐ型半導
体層中のドーパントがｐ型半導体層（３）全体に均一に
なるように含まれていて、ｎ型半導体層がn/i接合界面
でのドーパントの量が最も少なくなるように形成されて
いてもよく、ｐ型半導体層およびｎ型半導体層の両方の
ドーパントがそれぞれp/i、n/i接合界面で最低になるよ
うにされていてもよい。また、第１図においてはｐ型層
側から光（７）が入るようになっているが、光がｎ型層
側から入ってもよい。さらにはpin層は、１層である必
要もなく、２〜５層かさねて設けてもよい。この際、２
層目以上の層も上記のようにｉ層との接合界面のドーパ
ント量を最も少なくするようにしてもよく、第２図のよ
うな通常のpin層を設けてもよい。なお第２図の（８）
は通常のｐ型層である。In the semiconductor device of FIG. 1, the amount of dopant at the p / i junction interface is minimized, but the dopant in the p-type semiconductor layer is made uniform throughout the p-type semiconductor layer (3). And the n-type semiconductor layer may be formed so that the amount of the dopant at the n / i junction interface is the smallest, and the dopants of both the p-type semiconductor layer and the n-type semiconductor layer are respectively p-type. It may be made to be the lowest at the / i, n / i junction interface. Although light (7) enters from the p-type layer side in FIG. 1, light may enter from the n-type layer side. Furthermore, the pin layer does not have to be a single layer, and may be formed by stacking 2 to 5 layers. At this time, 2
As for the layers above the second layer, the amount of dopant at the junction interface with the i layer may be minimized as described above, or a normal pin layer as shown in FIG. 2 may be provided. Note that (8) in FIG.
Is a normal p-type layer.
ｐ型層あるいはｎ型層のドーパントの量としては、通
常0.01〜5atm％程度であるが、ドーパントの量が最も少
ないp/i接合界面あるいはn/i接合界面付近、好ましくは
該界面から少なくとも20〜30Å、さらに好ましくは少な
くとも100Åまでの部分のドーパントの量は0.01atm％以
下が好ましく、0.001atm％以下がさらに好ましい。な
お、本発明においてp/iまたはn/i接合面でのドーパント
量を0.001atm％以下が好ましいとしている理由は、前記
接合面でのドーパント量はなるべく少なく、０であるこ
とが好ましいが、アモルファスのSiC:Hにおいてはドー
パント量が0.001atm％以下であれば実質的に０に等し
く、また実際の製造においてはドーパント量をなかなか
０にすることが困難であった。そこで、チャンバー内の
汚れなどからくる予定しないわずかなドーパントを想定
し、しかも最善の実用性を考慮したからである。これら
のことは本発明者らによる半導体装置試作の結果から明
らかにされている。The amount of the dopant in the p-type layer or the n-type layer is usually about 0.01 to 5 atm%, but the p / i junction interface or the n / i junction interface having the smallest amount of the dopant is preferably at least 20% from the interface. The amount of the dopant in the portion up to 30 Å, more preferably at least 100 Å, is preferably 0.01 atm% or less, more preferably 0.001 atm% or less. In the present invention, the reason why the p / i or n / i junction face is preferably 0.001 atm% or less is because the amount of the dopant on the joint face is as small as possible, preferably 0, but amorphous. In the case of SiC: H, if the dopant amount is 0.001 atm% or less, it is substantially equal to 0, and it was difficult to reduce the dopant amount to 0 in actual production. Therefore, a small amount of dopant that is not expected due to dirt in the chamber is assumed, and the best practicality is taken into consideration. These facts have been clarified from the results of the trial manufacture of the semiconductor device by the present inventors.
ドーパントの分布はp/i接合界面あるいはn/i接合界面
からp/電極あるいはn/電極接合界面に向って段階的に増
加している必要があり、このような構成にすることによ
り、ｉ層へのドーパントの侵入が少なくなる、ｉ層とド
ーパント層の間の界面が改善されるなどの理由により、
結果的に開放電圧が増加するという効果がえられる。The distribution of the dopant must be increased stepwise from the p / i junction interface or n / i junction interface toward the p / electrode or n / electrode junction interface. For the reason that the penetration of the dopant into the dopant is reduced, the interface between the i layer and the dopant layer is improved, and the like.
As a result, the effect of increasing the open circuit voltage can be obtained.
本明細書にいう段階的に増加しているとは、通常のド
ーピング層から熱拡散によって生ずるしみだしにより自
然に生ずる増加ではなく、ドーパントの量を調整するこ
とによりえられる連続的な増加や段階状の増加などを意
味する。The term "incremental increase" as used herein means a continuous increase or step obtained by adjusting the amount of a dopant, not an increase naturally caused by a seepage caused by thermal diffusion from a usual doping layer. It means the increase of the state.
第３図はｐ型層がａ−SiC:H、ｉ型層がａ−Si:H、ｎ
型層がａ−Si:Hである本発明の半導体装置のドーパント
の分布の一実施態様に関する説明図である。第３図にお
いて、（９）はｐ型半導体層中のｐ型ドーパントの分布
を示すグラフ、（10）はｎ型半導体層中のｎ型ドーパン
トの分布を示すグラフ、（11）、（12）は従来の半導体
装置のｐ型ドーパント、ｎ型ドーパントの分布を示すグ
ラフである。In FIG. 3, the p-type layer is a-SiC: H, the i-type layer is a-Si: H, n.
It is explanatory drawing regarding one embodiment of distribution of the dopant of the semiconductor device of this invention whose type layer is a-Si: H. In FIG. 3, (9) is a graph showing the distribution of the p-type dopant in the p-type semiconductor layer, (10) is a graph showing the distribution of the n-type dopant in the n-type semiconductor layer, (11), (12) 3 is a graph showing distributions of p-type dopant and n-type dopant in a conventional semiconductor device.
ドーパントの分布は、第３図に示すようにｐ型層内ま
たはｎ型層内に分布すればよいが、かならずしも図の形
に限定されるものではない。要するにｐ型層またはｎ型
層中のドーパントの分布がp/iまたはn/i接合界面で最も
少なくなるようにすればよい。The dopant distribution may be distributed in the p-type layer or the n-type layer as shown in FIG. 3, but is not limited to the shape shown in the drawing. In short, the distribution of the dopant in the p-type layer or the n-type layer may be minimized at the p / i or n / i junction interface.
ａ−SiC:Hをドープ層として用いて本発明の半導体装
置を製造しようとすると、ドープなしのａ−SiC:Hの絶
縁層がp/iまたはn/i接合界面に存在することになるが、
このような構造でもよい。If an attempt is made to manufacture a semiconductor device of the present invention using a-SiC: H as a doped layer, an undoped a-SiC: H insulating layer exists at the p / i or n / i junction interface. ,
Such a structure may be used.
本発明に用いる電極にはとくに制限はなく、通常太陽
電池の作製に用いられるような透明電極、金属電極、シ
リサイド電極あるいはこれらの材料を多層構造にした電
極のごとき電極であれば用いうる。The electrode used in the present invention is not particularly limited, and may be any electrode such as a transparent electrode, a metal electrode, a silicide electrode which is usually used in the production of solar cells, or an electrode having a multilayer structure of these materials.
本発明における半導体を作製する装置としては、平行
平板容量結合型プラズマCVD装置、誘導結合型プラズマC
VD装置、熱CVD装置、ECRプラズマCVD装置、光CVD装置、
励起種CVD装置などがあげられるが、これらに限定され
るものではない。またその製造方法、原料などにもとく
に限定はない。As a device for producing a semiconductor in the present invention, a parallel plate capacitively coupled plasma CVD device, an inductively coupled plasma C
VD equipment, thermal CVD equipment, ECR plasma CVD equipment, optical CVD equipment,
Examples of the excited species CVD apparatus include, but are not limited to. Further, there is no particular limitation on the manufacturing method, raw material, or the like.
本発明におけるpin構造や、nip構造は非晶質半導体系
の光起電力素子やフォトダイオードなどで一般的に用い
られている構造である。The pin structure and the nip structure in the present invention are structures generally used in amorphous semiconductor-based photovoltaic elements, photodiodes, and the like.
以下、本発明の半導体装置を実施例に基づき説明す
る。Hereinafter, the semiconductor device of the present invention will be described based on examples.
実施例１および比較例１ 第１図に示す構造の太陽電池を試作した。Example 1 and Comparative Example 1 A solar cell having the structure shown in FIG.
基板としてはガラス上に透明電極としてSiO2をスパッ
タ法にて800Åの厚さに蒸着したものを用いた。As the substrate, a transparent electrode on which SiO 2 was vapor-deposited to a thickness of 800 Å was used as a transparent electrode.
この基板上にプラズマCVD法によりｐ型ａ−SiC:H膜を
150Å堆積させた。ｐ型ａ−SiC:Hの原料ガスとしてSi
H4、CH4、B2H6（H2で1000ppmに希釈したもの）を用い、
３つのガスの流量をそれぞれ10sccm、30sccm、200sccm
として一定のまま70Å堆積し、グロー放電を維持したま
ま、B2H6の量のみを徐々に減少させて、残りの80Åを堆
積するようにし、ｐ層堆積完了の時点ではB2H6の流量が
0sccmになるようにした。A p-type a-SiC: H film is formed on this substrate by the plasma CVD method.
150 Å deposited. Si as a source gas for p-type a-SiC: H
Using H 4 , CH 4 , and B 2 H 6 (diluted with H 2 to 1000 ppm),
Flow rate of 3 gases is 10sccm, 30sccm, 200sccm respectively
Remains constant and 70Å deposited as, while maintaining the glow discharge, it is gradually reduced only the amount of B 2 H 6, so as to deposit the remaining 80 Å, at the time of the p-layer deposition completion of B 2 H 6 Flow rate
It was set to 0 sccm.
続いてSiH4をグロー放電分解してｉ型ａ−Si:H層を約
7000Å、さらにSiH4 20sccm、H2で1000ppmに希釈したPH
3 100sccmの混合ガスをグロー放電分解して300Å堆積さ
せたのち、裏面の金属電極としてAlを1000Å真空蒸着法
にて蒸着し、1cm2の素子を作製した。Then, SiH 4 was decomposed by glow discharge to remove the i-type a-Si: H layer.
7,000Å, SiH 4 20sccm, PH diluted to 1000ppm with H 2
3 100 sccm of mixed gas was decomposed by glow discharge to deposit 300 Å, and then Al was evaporated by a 1000 Å vacuum evaporation method as a metal electrode on the back surface to fabricate a 1 cm 2 element.
B2H6を一定量流したときのｐ型層のドーパント量は2a
tm％であった。The dopant amount in the p-type layer is 2a when a certain amount of B 2 H 6 is flown.
It was tm%.
ｐ型ａ−SiC:Hを上記一定流量にて150Å堆積した他
は、上記と同様にして比較のために従来と同じ型の太陽
電池を作製した。For comparison, a solar cell of the same type as the conventional one was produced in the same manner as above, except that p-type a-SiC: H was deposited at a constant flow rate of 150Å.
えられた２種の太陽電池の螢光灯200lux下でのＶ−Ｉ
特性を測定した結果を第４に示す。VI of the obtained two types of solar cell fluorescent lamp under 200lux
Fourthly, the result of measuring the characteristics is shown.
比較例１の太陽電池の開放電圧が0.6V程度であるのに
対し、実施例１の太陽電池の開放電圧は0.70Vであっ
た。また電流、FFにも若干の向上が見られた。The open circuit voltage of the solar cell of Comparative Example 1 was about 0.6V, whereas the open circuit voltage of the solar cell of Example 1 was 0.70V. There was also a slight improvement in current and FF.
本発明の半導体装置は従来の半導体装置に比較して、
光照射下、とくに低照度光下において高い開放電圧を示
す。The semiconductor device of the present invention, compared to the conventional semiconductor device,
It shows a high open circuit voltage under light irradiation, especially under low illuminance light.
第１図は本発明の半導体装置の一実施態様に関する説明
図、第２図は従来の半導体装置の一実施態様に関する説
明図、第３図は本発明に用いるpin型半導体層中におけ
るドーパントの分布の一例と、従来のpin型半導体層中
におけるドーパントの分布の一例とに関する説明図、第
４図は実施例１および比較例１でえられた太陽電池のＶ
−Ｉ特性を示すグラフである。 （図面の主要符号） （２）：透明電極 （３）:p型層 （４）:i型層 （５）:n型層 （６）：裏面電極FIG. 1 is an explanatory view of an embodiment of a semiconductor device of the present invention, FIG. 2 is an explanatory view of an embodiment of a conventional semiconductor device, and FIG. 3 is a distribution of a dopant in a pin type semiconductor layer used in the present invention. And an example of a conventional dopant distribution in a pin-type semiconductor layer, and FIG. 4 shows V of the solar cells obtained in Example 1 and Comparative Example 1.
It is a graph which shows -I characteristic. (Main symbols in the drawing) (2): Transparent electrode (3): p-type layer (4): i-type layer (5): n-type layer (6): Back electrode
───────────────────────────────────────────────────── フロントページの続き (72)発明者 太和田 善久 神戸市北区大池見山台14―39 (56)参考文献 特開 昭56−150876（ＪＰ，Ａ) 特開 昭59−14679（ＪＰ，Ａ) 特開 昭59−96775（ＪＰ，Ａ) 特開 昭60−50973（ＪＰ，Ａ) 特開 昭59−163876（ＪＰ，Ａ) 特開 昭58−106876（ＪＰ，Ａ) 「アモルファス太陽電池」（株）昭晃 堂昭和58年８月15日発行ＰＰ．164〜169 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Yoshihisa Owada 14-39 Oikemiyamadai, Kita-ku, Kobe (56) References JP-A-56-150876 (JP, A) JP-A-59-14679 (JP, A) JP 59-96775 (JP, A) JP 60-50973 (JP, A) JP 59-163876 (JP, A) JP 58-106876 (JP, A) "Amorphous solar cell "Shokido Co., Ltd. Published on August 15, 1983 PP. 164-169
Claims (5)
も２つの電極とを有する半導体装置において、ｐ型層ま
たはｎ型層のドーパントの量がp/電極またはn/電極接合
界面からp/iまたはn/i接合界面に向かって段階的に減少
し当該p/iまたはn/i接合界面で実質的にゼロになるよう
に、p/iまたはn/i接合界面に向かうにしたがいドーパン
トの導入量を段階的に減少せしめてなる部分をｐ型層ま
たはｎ型層の少なくとも１つに設けており、前記ｐ型層
またはｎ型層のうちドーパント量が段階的に変化してい
る層が一定組成のａ−SiC:H層であることを特徴とする
半導体装置。1. In a semiconductor device having a semiconductor layer containing pin-type amorphous material and at least two electrodes, the amount of dopant in the p-type layer or n-type layer is p / electrode or n / electrode junction interface. dopant toward the p / i or n / i junction interface so that it gradually decreases toward the / i or n / i junction interface and becomes substantially zero at the p / i or n / i junction interface. A layer in which the amount of introduction of the element is reduced in at least one of the p-type layer or the n-type layer, and the dopant amount in the p-type layer or the n-type layer is changed stepwise. Is a a-SiC: H layer having a constant composition.
合界面から少なくとも20Åまでの厚さの部分において、
前記界面からp/電極またはn/電極接合界面に向けてドー
パントの量が段階的に増加している特許請求の範囲第１
項記載の半導体装置。2. A portion of the p-type layer or the n-type layer having a thickness of at least 20Å from the p / i or n / i junction interface,
The amount of dopant is increased stepwise from the interface toward the p / electrode or n / electrode junction interface.
The semiconductor device according to the item.
合界面から少なくとも100Åまでの厚さの部分におい
て、前記界面からp/電極またはn/電極接合界面に向けて
ドーパントの量が段階的に増加している特許請求の範囲
第１項記載の半導体装置。3. A dopant having a thickness of at least 100Å from the p / i or n / i junction interface of the p-type layer or the n-type layer toward the p / electrode or n / electrode junction interface. The semiconductor device according to claim 1, wherein the amount of the electric field is increased stepwise.
族に属する元素（Ｂ、Al、Ga、In、Tl）である特許請求
の範囲第１項、第２項または第３項記載の半導体装置。4. The dopant of the p-type layer is a periodic table IIIa.
The semiconductor device according to claim 1, 2, or 3, which is an element belonging to the group (B, Al, Ga, In, Tl).
に属する元素（Ｎ、Ｐ、As、Sb、Te、Po）である特許請
求の範囲第１項、第２項または第３項記載の半導体装
置。5. The dopant according to claim 1, wherein the dopant of the n-type layer is an element (N, P, As, Sb, Te, Po) belonging to Group V a of the periodic table. The semiconductor device according to the item.
Priority Applications (12)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60255681A JP2545066B2 (en) | 1985-11-14 | 1985-11-14 | Semiconductor device |
| CA000521602A CA1321660C (en) | 1985-11-05 | 1986-10-28 | Amorphous-containing semiconductor device with high resistivity interlayer or with highly doped interlayer |
| AU64619/86A AU600453B2 (en) | 1985-11-05 | 1986-10-31 | Semiconductor device |
| DE3650012T DE3650012T2 (en) | 1985-11-05 | 1986-11-01 | Semiconductor device. |
| EP86115170A EP0221523B1 (en) | 1985-11-05 | 1986-11-01 | Semiconductor device |
| EP19920104633 EP0494090A3 (en) | 1985-11-05 | 1986-11-01 | Photovoltaic device |
| DE3650712T DE3650712T2 (en) | 1985-11-05 | 1986-11-01 | Photovoltaic device |
| EP92104628A EP0494088B1 (en) | 1985-11-05 | 1986-11-01 | Photovoltaic device |
| CN86106353A CN1036817C (en) | 1985-11-05 | 1986-11-05 | Semiconductor device |
| KR860009364A KR870005477A (en) | 1985-11-05 | 1986-11-05 | Semiconductor devices |
| US07/477,138 US5032884A (en) | 1985-11-05 | 1990-02-07 | Semiconductor pin device with interlayer or dopant gradient |
| AU65966/90A AU636677B2 (en) | 1985-11-05 | 1990-11-09 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60255681A JP2545066B2 (en) | 1985-11-14 | 1985-11-14 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62115785A JPS62115785A (en) | 1987-05-27 |
| JP2545066B2 true JP2545066B2 (en) | 1996-10-16 |
Family
ID=17282146
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60255681A Expired - Lifetime JP2545066B2 (en) | 1985-11-05 | 1985-11-14 | Semiconductor device |
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| Country | Link |
|---|---|
| JP (1) | JP2545066B2 (en) |
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| KR101207582B1 (en) * | 2009-02-17 | 2012-12-05 | 한국생산기술연구원 | Method for fabricating solar cell applications using inductively coupled plasma chemical vapor deposition |
| JP2013125891A (en) * | 2011-12-15 | 2013-06-24 | Sharp Corp | Photoelectric conversion element and manufacturing method of the same |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56150876A (en) * | 1980-04-24 | 1981-11-21 | Sanyo Electric Co Ltd | Photovoltaic device |
| JPS5914679A (en) * | 1982-07-16 | 1984-01-25 | Toshiba Corp | Photovoltaic device |
| JPS5996775A (en) * | 1982-11-25 | 1984-06-04 | Agency Of Ind Science & Technol | Amorphous silicon photoelectric conversion device |
| JPH0658970B2 (en) * | 1983-08-31 | 1994-08-03 | 工業技術院長 | Semiconductor device |
-
1985
- 1985-11-14 JP JP60255681A patent/JP2545066B2/en not_active Expired - Lifetime
Non-Patent Citations (1)
| Title |
|---|
| 「アモルファス太陽電池」（株）昭晃堂昭和５８年８月１５日発行ＰＰ．１６４〜１６９ |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62115785A (en) | 1987-05-27 |
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