JPH0719906B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JPH0719906B2 JPH0719906B2 JP59152531A JP15253184A JPH0719906B2 JP H0719906 B2 JPH0719906 B2 JP H0719906B2 JP 59152531 A JP59152531 A JP 59152531A JP 15253184 A JP15253184 A JP 15253184A JP H0719906 B2 JPH0719906 B2 JP H0719906B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- doped layer
- impurity
- temperature
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02529—Silicon carbide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02587—Structure
- H01L21/0259—Microstructure
- H01L21/02592—Microstructure amorphous
Description
【発明の詳細な説明】 ［産業上の利用分野］ 本発明は半導体装置の製造方法に関する。The present invention relates to a method for manufacturing a semiconductor device.
［従来の技術］ 太陽電池などに用いられるa-Si:H、a-SiC:H、a-Ge:H、a
-Si:F:H、μC-Si:Hなどの非晶質シリコン膜を成膜する
際に、通常容量結合型RF平行平板CVD装置が用いられて
いる。[Prior Art] a-Si: H, a-SiC: H, a-Ge: H, a used in solar cells
When forming an amorphous silicon film such as -Si: F: H or μC-Si: H, a capacitive coupling type RF parallel plate CVD apparatus is usually used.
しかし、この装置を用い、従来法のように220〜250℃程
度の温度で成膜すると、電子や半導体形成ガスから生成
されたラジカルが直接基板面に衝突するため、ITO、In2
O3、ITO/SnO2、CdXSnOY（ｘ＝0.5〜２、ｙ＝２〜４）、
IrXO1-X（ｘ＝0.33〜0.5）などから形成された透明導電
膜が一部還元され、金属化する。この金属が堆積された
第１不純物ドープ層のみならず真性層まで拡散して、一
種のドーパントとして作用したり、真性層で発生した電
子やホールを打消してしまう再結合中心になったりする
など、半導体／透明導電膜間の界面が著しく劣化する。
また、前記金属化が生じると、透明電極そのものの透明
性や導電性も低下するため、半導体装置の特性、とくに
光電変換特性が大幅に低下する。However, using this apparatus, when formed at a temperature of about 220 to 250 ° C. as in the conventional method, because the radicals generated from electronic or semiconductor forming gas impinging directly on the substrate surface, ITO, an In 2
O 3 , ITO / SnO 2 , Cd X SnO Y (x = 0.5 to 2, y = 2 to 4),
The transparent conductive film formed of Ir X O 1-X (x = 0.33 to 0.5) or the like is partially reduced and metallized. This metal diffuses not only into the first impurity-doped layer in which it is deposited, but also into the intrinsic layer and acts as a kind of dopant, or becomes a recombination center that cancels the electrons and holes generated in the intrinsic layer. , The interface between the semiconductor and the transparent conductive film is significantly deteriorated.
Further, when the metallization occurs, the transparency and the conductivity of the transparent electrode itself are also lowered, so that the characteristics of the semiconductor device, particularly the photoelectric conversion characteristics are significantly lowered.
［発明が解決しようとする問題点］ 本発明は、前記のごとき酸化物透明導電膜上に非晶質半
導体を堆積する際におこる、酸化物透明導電膜の還元に
より生ずる問題を少なくしようとするものである。[Problems to be Solved by the Invention] The present invention seeks to reduce the problems caused by the reduction of an oxide transparent conductive film, which occurs when an amorphous semiconductor is deposited on an oxide transparent conductive film as described above. It is a thing.
［問題点を解決するための手段］ 本発明は、酸化物透明導電膜上に第１不純物ドープ層
（以下、第１ドープ層という）、真性層、第２不純物ド
ープ層（以下、第２ドープ層という、第１ドープ層と反
対の導電タイプ）からなる非晶質半導体をこの順に堆積
する際に、第１ドープ層の成膜温度を10〜130℃、真性
層および第２不純物ドープ層の成膜温度を160〜350℃に
し、第１不純物ドープ層をドープしたa-SiC:H層にする
ことにより、前記問題を少なくしたものである。[Means for Solving Problems] The present invention provides a first impurity-doped layer (hereinafter referred to as a first doped layer), an intrinsic layer, and a second impurity-doped layer (hereinafter referred to as a second doped layer) on an oxide transparent conductive film. Layer, the amorphous semiconductor of the opposite conductivity type to the first doped layer) is deposited in this order, the deposition temperature of the first doped layer is 10 to 130 ° C., the intrinsic layer and the second impurity doped layer are The above problem is reduced by setting the film forming temperature to 160 to 350 ° C. and using the doped first impurity-doped layer as an a-SiC: H layer.
［実施例］ 本発明に用いる酸化物透明導電膜とは一般に半導体装置
の製造に使用される、厚さ0.01〜10μｍ程度の酸化物透
明導電膜のことであり、このような酸化物透明導電膜で
ある限り、とくに限定はない。該導電膜の具体例として
は、ITO、ITO/SnO2、In2O3、SnO2、CdXSnOY（ｘ＝0.5〜
２、ｙ＝２〜４）、IrXO1-X（ｘ＝0.33〜0.5）、CdOな
どがあげられるが、これらに限定されるものではない。[Examples] The oxide transparent conductive film used in the present invention is an oxide transparent conductive film having a thickness of about 0.01 to 10 µm, which is generally used for manufacturing a semiconductor device. There is no particular limitation as long as Specific examples of the conductive film include ITO, ITO / SnO 2 , In 2 O 3 , SnO 2 , Cd X SnO Y (x = 0.5 to
2, y = 2~4), Ir X O 1-X (x = 0.33~0.5), but such CdO and the like, but is not limited thereto.
これらの導電膜はいずれも、水素原子を含んだような還
元性のプラズマにより還元されやすく、とくに温度が高
くなると一般的な化学反応のばあいと同様、その還元が
顕著におこる。All of these conductive films are easily reduced by a reducing plasma containing hydrogen atoms, and the reduction is remarkable at a high temperature as in a general chemical reaction.
本発明において酸化物透明導電膜上に堆積される際１ド
ープ層は、a-SiC:Hのｐ型のものが一般的に用いられる
が、このようなｐ型のドープ層に限定されるものではな
い。In the present invention, as the 1-doped layer deposited on the transparent conductive oxide film, a-SiC: H p-type layer is generally used, but it is limited to such p-type doped layer. is not.
第１ドープ層が堆積されたのちに形成される真性層、お
よび第２ドープ層としては、通常用いられる真性層、お
よび第１ドープ層と反対の導電タイプである第２ドープ
層であれば、とくに限定されるものではない。このよう
な真性層の具体例としては、a-Si:H、a-Si:F、a-Si:F:
H、a-SiGe:H、a-SiSn:H、a-SiN:Hなど、第２ドープ層の
具体例としては、第１ドープ層がｐ型のばあいにはｎ型
のμC-Si:H、a-SiC:H、a-Si:H、a-SiN:Hなど、第１ドー
プ層がｎ型のばあいにはｐ型のa-Si:H、μC-Si:H、a-Si
C:Hなどがあげられる。As the intrinsic layer formed after the first doped layer is deposited and the second doped layer, a normally used intrinsic layer and a second doped layer having a conductivity type opposite to that of the first doped layer, It is not particularly limited. Specific examples of such an intrinsic layer include a-Si: H, a-Si: F, and a-Si: F:
Specific examples of the second doped layer such as H, a-SiGe: H, a-SiSn: H, and a-SiN: H include n-type μC-Si: when the first doped layer is p-type. When the first doped layer is n-type such as H, a-SiC: H, a-Si: H, and a-SiN: H, p-type a-Si: H, μC-Si: H, a- Si
Examples include C: H.
本発明においては、第１ドープ層を成膜するばあい成膜
温度を130℃以下、好ましくは150℃以下、さらに好まし
くは130℃以下、ことにヒーターを用いない温度（たと
えば10〜70℃程度）、とくに好ましくは基板を冷却した
温度（たとえば10〜40℃程度）にするのがよい。このよ
うに成膜温度を低くして成膜することにより、酸化物透
明導電膜が水素原子を含んだ還元性のプラズマと接触し
ても還元されにくくなり、したがって生成する金属の量
も少なくなり、該金属による半導体層の汚染から生ずる
再結合中心の発生、ドーピング効率の低下などの半導体
特性の低下が著しく改善される。また低い温度で成膜す
るので堆積される第１ドープ層に発生する内部応力を少
なくすることができるため、第１ドープ層／酸化物透明
導電膜の界面におけるストレスから起因するダングリン
グボンドなどの欠陥を減少させることができる。さらに
連続プロセス装置を用いてヒーターを用いない温度で成
膜するようなばあいには、ヒーターの１つを節約するこ
とができ、装置コストの低減をはかることができる。In the present invention, when forming the first dope layer, the film forming temperature is 130 ° C. or lower, preferably 150 ° C. or lower, more preferably 130 ° C. or lower, especially a temperature not using a heater (for example, about 10 to 70 ° C.). ), Particularly preferably, the substrate is cooled to a temperature (for example, about 10 to 40 ° C.). By thus forming the film at a low film formation temperature, it becomes difficult for the oxide transparent conductive film to be reduced even when it is brought into contact with a reducing plasma containing hydrogen atoms, and thus the amount of metal produced is also reduced. The deterioration of semiconductor characteristics such as the generation of recombination centers and the deterioration of doping efficiency resulting from the contamination of the semiconductor layer by the metal is remarkably improved. Further, since the film is formed at a low temperature, the internal stress generated in the deposited first doped layer can be reduced, so that the dangling bond or the like caused by the stress at the interface between the first doped layer and the transparent oxide conductive film can be reduced. Defects can be reduced. Further, in the case where a film is formed using a continuous process device at a temperature without using a heater, one of the heaters can be saved and the cost of the device can be reduced.
前記第１ドープ層を成膜するばあいのプラズマ条件は成
膜温度が低いために注意を要し、通常圧力を0.2〜2.5To
rrの範囲で、グロー放電を維持可能な最小またはその近
傍の圧力にし、シランとメタンの混合ガスに対するドー
ピングガスの流量比を0.05〜2.0％にし、RFパワーはグ
ロー放電を維持可能な範囲（５〜20W/cm2）で最小にな
るようにして、膜のドーピング特性、光学的禁止帯幅を
最適化した条件、たとえばｐ型半導体を製造するばあい
には、導電率の温度依存性から求まる活性化エネルギー
ΔＥが0.6eV以下、光学的禁止帯幅Eoptとの差がEopt−
ΔＥ1.3eVになるように最適化された条件である。When forming the first doped layer, be careful of the plasma condition that the film forming temperature is low.
Within the range of rr, the pressure is set to the minimum or a level near which the glow discharge can be maintained, the flow rate ratio of the doping gas to the mixed gas of silane and methane is set to 0.05 to 2.0%, and the RF power is within the range (5 -20 W / cm 2 ) to minimize the doping characteristics of the film and the optical bandgap, for example, when manufacturing a p-type semiconductor, it is determined from the temperature dependence of conductivity. The activation energy ΔE is 0.6 eV or less, and the difference from the optical bandgap Eopt is Eopt−
This is the condition optimized to be ΔE 1.3 eV.
なお本発明の方法を実施するための装置としては、通常
の容量結合型RF平行平板CVD装置、誘導結合型RF平行平
板CVD装置、DC平行平板型CVD装置などがあげられるが、
平行平板CDV装置に顕著な効果がみられる。Examples of the apparatus for carrying out the method of the present invention include a usual capacitively coupled RF parallel plate CVD apparatus, an inductively coupled RF parallel plate CVD apparatus, a DC parallel plate CVD apparatus, and the like.
The parallel plate CDV device has a remarkable effect.
つぎに本発明の方法を実施例に基づき説明する。Next, the method of the present invention will be described based on examples.
実施例１〜４および比較例１〜３ RF容量結合型平行平板CVD装置を用い、青板ガラス板上
にスパッタ法により厚さ700ÅになるようにITOを形成し
た。第１表に示す温度、CVD圧力1.5Torr、SiH4／CH4の
流量が2/3、SiH4＋CH4の合計流量に対してB2H6の流量に
なるようにして、RFパワー密度10mW/cm2でｐ型a-SiC:H
層をITO面上に100Å堆積させたのち、220℃、CVD圧力1T
orr、SiH4ガスを用いてRFパワー密度15mW/cm2でｉ型a-S
i:H層を6000Å堆積させた。ついで220℃、CVD圧力2Tor
r、SiH4に対しPH3が１％、H2が30倍になるように導入
し、RFパワー密度50〜70mW/cm2でｎ型μC-Si:H層を300
Å堆積させ、電極としてAlを真空蒸着法により1000Å堆
積させて、１cm2の面積を有する太陽電池を作製した。Examples 1 to 4 and Comparative Examples 1 to 3 ITO was formed on a soda-lime glass plate by sputtering to a thickness of 700 Å using an RF capacitive coupling type parallel plate CVD apparatus. The RF power density is 10mW at the temperature shown in Table 1, the CVD pressure is 1.5Torr, the SiH 4 / CH 4 flow rate is 2/3, and the total flow rate of SiH 4 + CH 4 is B 2 H 6. / cm 2 p-type a-SiC: H
After depositing 100 Å layer on ITO surface, 220 ℃, CVD pressure 1T
i-type aS with RF power density of 15 mW / cm 2 using orr and SiH 4 gas
An i: H layer was deposited at 6000Å. Then 220 ° C, CVD pressure 2 Tor
Introduced so that PH 3 is 1% and H 2 is 30 times that of r and SiH 4 , and the n-type μC-Si: H layer is 300 at RF power density of 50 to 70 mW / cm 2.
Å was deposited, and Al was deposited as an electrode by 1000 Å by a vacuum vapor deposition method to fabricate a solar cell having an area of 1 cm 2 .
えられた太陽電池の特性をAM-1、100mW/cm2のソーラー
シュレーターを用いて測定した。それらの結果を第１表
および第１図に示す。The characteristics of the obtained solar cell were measured by using AM-1, 100 mW / cm 2 solar insulator. The results are shown in Table 1 and FIG.
酸化物透明電極/p層/i層の界面の様子をしらべるため、
えられた太陽電池と同じCVD条件にてｐ層およびｉ層をI
TO上にそれぞれ100Å、300Åの厚さに順次堆積されたの
ちESCA、Anger、SIMSなどの電子分光法により測定し、
ｐ層およびｉ層に拡散したInの量を分析した。それらの
結果を第１表に示す。In order to investigate the state of the oxide transparent electrode / p layer / i layer interface,
Under the same CVD conditions as the obtained solar cell, p layer and i layer
After being sequentially deposited on the TO to a thickness of 100 Å and 300 Å respectively, they are measured by electron spectroscopy such as ESCA, Anger and SIMS,
The amount of In diffused in the p and i layers was analyzed. The results are shown in Table 1.
第１表の結果から、ｐ層の成膜温度を下げることによ
り、太陽電池特性のうちの短絡電流（JSC）および曲線
因子（FF）に大幅な改善がみられ、結果的に光電変換効
率（η）の向上がはかられることがわかる。 From the results in Table 1, by lowering the film formation temperature of the p-layer, the short-circuit current (JSC) and fill factor (FF) of the solar cell characteristics were significantly improved, and as a result, the photoelectric conversion efficiency ( It can be seen that η) can be improved.
また第１表の結果から、ｐ層およびｉ層に拡散したInの
量が、成膜温度30℃のものは、180℃のものの1/10以
下、225℃のものの1/20以下であることがわかる。From the results shown in Table 1, the amount of In diffused into the p-layer and i-layer should be 1/10 or less of 180 ° C. and 1/20 or less of 225 ° C. at the film forming temperature of 30 ° C. I understand.
［発明の効果］ 本発明の方法により半導体装置を製造すると、低い温度
で第１ドープ層を成膜するため、酸化物透明導電膜が水
素原子を含んだような還元性のプラズマと接触しても還
元されにくくなり、したがって生成する金属の量も少な
くなり、該金属による再結合中心の増加、ドーピング特
性の低下などの半導体特性の低下が著しく改善される。
また低温度で成膜するために堆積される１ドープ層に発
生する内部応力を少なくすることができるため、第１ド
ープ層／酸化物透明導電膜の界面における応力により発
生するダングリングボンドなどの欠陥を減少させること
ができる。さらに連続プロセス装置を用いてヒーターを
使用しない温度で成膜するようなばあいには、ヒーター
の１つを節約することができ、装置コストの低減をはか
ることができる。[Effects of the Invention] When a semiconductor device is manufactured by the method of the present invention, the first doped layer is formed at a low temperature, so that the oxide transparent conductive film is brought into contact with a reducing plasma containing hydrogen atoms. Is less likely to be reduced, and therefore the amount of metal produced is reduced, and the deterioration of semiconductor properties such as the increase of recombination centers and the deterioration of doping properties due to the metal is remarkably improved.
In addition, since the internal stress generated in the 1-doped layer deposited to form a film at a low temperature can be reduced, the dangling bond or the like generated by the stress at the interface between the 1st doped layer and the transparent oxide conductive film can be reduced. Defects can be reduced. Further, in the case where a film is formed using a continuous process device at a temperature where a heater is not used, one of the heaters can be saved and the cost of the device can be reduced.
第１図は実施例１〜４および比較例１〜２でえられた太
陽電池の特性を示したグラフである。FIG. 1 is a graph showing the characteristics of the solar cells obtained in Examples 1 to 4 and Comparative Examples 1 and 2.
フロントページの続き (72)発明者 西村 国夫 京都府京都市下京区仏光寺通西洞院西入ル 木賊山町187 (72)発明者 津下 和永 兵庫県神戸市垂水区舞子台６丁目６―5111 (72)発明者 太和田 善久 兵庫県神戸市北区大池見山台14―39 (56)参考文献 第29回応物連合大会予稿集（1982−４− １）、518頁（講演番号４Ｐ−Ｚ−５) 信学技報78［215］（1979−１−19）23 −30頁 電子材料1983年４月号 96−104頁Front page continuation (72) Kunio Nishimura Inventor Kunio Nishimura 187 Kiiriyamacho, Saitoin, Bukkoji-dori, Shimogyo-ku, Kyoto-shi, Kyoto (72) Kaninaga Tsushita 6-6-5111 Maikodai, Tarumi-ku, Kobe-shi, Hyogo (72) Inventor Yoshihisa Owada 14-39, Oikemiyamadai, Kita-ku, Kobe-shi, Hyogo (56) References Proceedings of the 29th Obi Association Conference (1982-4-1), page 518 (Lecture number 4P-Z- 5) IEICE Technical Report 78 [215] (1979-1-19) pages 23-30 Electronic Materials April 1983 pages 96-104
Claims (3)
層、真性層、第２不純物ドープ層（第１不純物ドープ層
と反対の導電タイプ）からなる非晶質半導体をこの順に
堆積する際に、第１不純物ドープ層の成膜温度が10〜13
0℃で、真性層および第２不純物ドープ層の成膜温度が1
60〜350℃であり、第１不純物ドープ層がドープしたa-S
iC:H層であることを特徴とする半導体装置の製造方法。1. When depositing an amorphous semiconductor comprising a first impurity-doped layer, an intrinsic layer, and a second impurity-doped layer (a conductivity type opposite to that of the first impurity-doped layer) on an oxide transparent conductive film in this order. And the deposition temperature of the first impurity-doped layer is 10 to 13
At 0 ° C, the film formation temperature of the intrinsic layer and the second impurity-doped layer is 1
60 to 350 ° C., aS doped with the first impurity-doped layer
A method for manufacturing a semiconductor device, which is an iC: H layer.
ターを用いない温度である特許請求の範囲第１項記載の
製造方法。2. The manufacturing method according to claim 1, wherein the film forming temperature of the first impurity-doped layer is a temperature at which a heater is not used.
を冷却した温度である特許請求の範囲第１項記載の製造
方法。3. The manufacturing method according to claim 1, wherein the film forming temperature of the first impurity-doped layer is a temperature at which the substrate is cooled.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59152531A JPH0719906B2 (en) | 1984-07-23 | 1984-07-23 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59152531A JPH0719906B2 (en) | 1984-07-23 | 1984-07-23 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6132416A JPS6132416A (en) | 1986-02-15 |
| JPH0719906B2 true JPH0719906B2 (en) | 1995-03-06 |
Family
ID=15542473
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59152531A Expired - Lifetime JPH0719906B2 (en) | 1984-07-23 | 1984-07-23 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0719906B2 (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01149968A (en) * | 1987-12-07 | 1989-06-13 | Toshiba Corp | Manufacture of fiber sliding member |
| JP3057886B2 (en) * | 1991-04-01 | 2000-07-04 | 株式会社豊田自動織機製作所 | Reed for weft insertion device in jet loom and method of manufacturing the reed |
| JPH0525754A (en) * | 1991-07-10 | 1993-02-02 | Tsudakoma Corp | Warp yarn sheet-arranging device and reed controller |
| AU767161B2 (en) | 1999-08-20 | 2003-10-30 | Kaneka Corporation | Method and apparatus for manufacturing semiconductor device |
| JP2002246619A (en) * | 2001-02-13 | 2002-08-30 | Kanegafuchi Chem Ind Co Ltd | Method of manufacturing thin film photoelectric conversion device |
| US10024065B2 (en) | 2009-03-27 | 2018-07-17 | Afi Licensing Llc | Floor panel and floating floor system incorporating the same |
-
1984
- 1984-07-23 JP JP59152531A patent/JPH0719906B2/en not_active Expired - Lifetime
Non-Patent Citations (3)
| Title |
|---|
| 信学技報７８［２１５（１９７９−１−１９）２３−３０頁 |
| 第２９回応物連合大会予稿集（１９８２−４−１）、５１８頁（講演番号４Ｐ−Ｚ−５） |
| 電子材料１９８３年４月号９６−１０４頁 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6132416A (en) | 1986-02-15 |
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