JPH071752B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

Info

Publication number
JPH071752B2
JPH071752B2 JP60091736A JP9173685A JPH071752B2 JP H071752 B2 JPH071752 B2 JP H071752B2 JP 60091736 A JP60091736 A JP 60091736A JP 9173685 A JP9173685 A JP 9173685A JP H071752 B2 JPH071752 B2 JP H071752B2
Authority
JP
Japan
Prior art keywords
layer
doped layer
deposited
impurity
intrinsic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP60091736A
Other languages
Japanese (ja)
Other versions
JPS61251020A (en
Inventor
正隆 近藤
和永 津下
善久 太和田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kaneka Corp
Original Assignee
Kaneka Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kaneka Corp filed Critical Kaneka Corp
Priority to JP60091736A priority Critical patent/JPH071752B2/en
Publication of JPS61251020A publication Critical patent/JPS61251020A/en
Publication of JPH071752B2 publication Critical patent/JPH071752B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02532Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/0262Reduction or decomposition of gaseous compounds, e.g. CVD

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は半導体装置の製造方法に関する。The present invention relates to a method for manufacturing a semiconductor device.

[従来の技術] 非晶質半導体層を含む太陽電池などの半導体装置の材料
として、a-Si:H、a-SiC:H、a-SiGe:H、a-SiN:H、a-Si:
F:H、a-Ge:Hなどや、これらの微結晶半導体などが用い
られている。これらの成膜はRFまたはDCのプラズマCVD
装置を用いて行なうのが通常である。
[Prior Art] As materials for semiconductor devices such as solar cells including an amorphous semiconductor layer, a-Si: H, a-SiC: H, a-SiGe: H, a-SiN: H, a-Si:
F: H, a-Ge: H, and the like, and microcrystalline semiconductors thereof are used. These depositions are RF or DC plasma CVD
It is usually done using a device.

従来法では、この種の装置を用いて220℃前後以上の成
膜温度ですべての非晶質半導体層を堆積させている。
In the conventional method, all amorphous semiconductor layers are deposited at a film forming temperature of about 220 ° C. or higher using this type of apparatus.

[発明が解決しようとする問題点] 透明導電膜上にこのような方法で半導体層を成膜する
と、プラズマ中の電子や、半導体形成ガスの分解生成物
であるイオンやラジカルなどが基板面に直接衝突するた
め、ITO、In2O3、ITO/SnO2、Cdx Sn Oy(X=0.5〜2、
Y=2〜4)、Irz O1-z(z=0.33〜0.5)などから形
成された透明導電膜が、一部または全体にわたって還元
され金属化する。この現象は第1不純物ドープ層堆積後
の真性層の堆積プロセスにおいても、成膜温度が220℃
前後あるいはこれ以上のばあいには第1不純物ドープ層
のすき間(第1ドープ層はうすいのが一般的で島状に形
成されやすく島間にすきまがある)を通して、電子やイ
オンやラジカルなどが基板面に衝突するため生ずる。
[Problems to be Solved by the Invention] When a semiconductor layer is formed on a transparent conductive film by such a method, electrons in plasma and ions or radicals which are decomposition products of a semiconductor forming gas are deposited on the substrate surface. Because of direct collision, ITO, In 2 O 3 , ITO / SnO 2 , Cd x Sn Oy (X = 0.5 to 2,
The transparent conductive film formed of Y = 2 to 4), Ir z O 1-z (z = 0.33 to 0.5) or the like is partially or wholly reduced and metallized. This phenomenon occurs even at the film forming temperature of 220 ° C. even in the process of depositing the intrinsic layer after depositing the first impurity-doped layer.
Before and after or more than this, electrons, ions, radicals, etc. are transferred to the substrate through the gaps in the first impurity-doped layer (the first doped layer is generally thin and is easily formed into islands and has a gap between islands). It occurs because it collides with a surface.

このようにして生成した金属は、堆積された第1不純物
ドープ層のみならず真性層にまで拡散して、一種のドー
パントとして作用したり、真性層で発生した電子やホー
ルを打消してしまう再結合中心になったりするため、半
導体/透明導電膜の界面や第1不純物ドープ層/真性層
の界面が著しく劣化する。
The metal generated in this way diffuses not only into the deposited first impurity-doped layer but also into the intrinsic layer, and acts as a kind of dopant or cancels out electrons and holes generated in the intrinsic layer. Since it becomes a bonding center, the interface between the semiconductor / transparent conductive film and the interface between the first impurity-doped layer / intrinsic layer are significantly deteriorated.

この拡散は、第1不純物ドープ層の堆積中のみならず真
性層堆積中にも進行するが、真性層堆積中にはさらに第
1不純物ドープ層のドーパント原子の拡散も進行する。
This diffusion progresses not only during the deposition of the first impurity-doped layer but also during the intrinsic layer deposition, but during the intrinsic layer deposition, the diffusion of the dopant atoms of the first impurity-doped layer also proceeds.

さらに前記金属化が生じると、透明導電膜そのものの導
電性や透明性も低下するため、半導体装置の特性、とく
に光電変換特性が大幅に低下する。
Further, when the metallization occurs, the conductivity and the transparency of the transparent conductive film itself are also lowered, so that the characteristics of the semiconductor device, particularly the photoelectric conversion characteristics are significantly lowered.

本発明は前記のごとき透明導電膜上に非晶質半導体を堆
積する際におこる透明導電膜の変質により生ずる問題を
少なくしようとするものであり、さらに第1不純物ドー
プ層と真性層との間の内蔵電界を強めることにより前記
再結合中心の影響を低減せんとするものである。
The present invention is intended to reduce the problems caused by the alteration of the transparent conductive film that occurs when the amorphous semiconductor is deposited on the transparent conductive film as described above, and further, to reduce the problem between the first impurity-doped layer and the intrinsic layer. The effect of the recombination center is reduced by strengthening the built-in electric field of.

[問題点を解決するための手段] 本発明は、透明導電膜上に非晶質半導体を第1不純物ド
ープ層(以下、第1ドープ層という)、真性層、第1ド
ープ層と反対の導電タイプの第2不純物ドープ層(以
下、第2ドープ層という)の順に堆積する際に、真性層
の一部として堆積せしめられる第1ドープ層に接する部
分から80Åの厚さの部分までの半導体層の堆積時の最高
成膜温度が、そののち成膜される真性層の最高成膜温度
より20〜250℃低い10〜180℃で成膜されることを特徴と
する半導体装置の製造方法に関する。
[Means for Solving Problems] In the present invention, an amorphous semiconductor is provided on a transparent conductive film as a first impurity-doped layer (hereinafter, referred to as a first doped layer), an intrinsic layer, and a conductivity opposite to that of the first doped layer. Type second impurity-doped layer (hereinafter referred to as the second doped layer), a semiconductor layer from a portion in contact with the first doped layer that is deposited as a part of the intrinsic layer to a portion having a thickness of 80 Å when deposited in this order. The present invention relates to a method for manufacturing a semiconductor device, wherein the maximum film forming temperature during deposition is 10 to 180 ° C., which is 20 to 250 ° C. lower than the maximum film forming temperature of the intrinsic layer to be formed thereafter.

[実施例] 本発明に用いる透明導電膜とは、半導体装置の製造に一
般に使用される厚さ0.01〜1.0μm程度の透明導電膜の
ことであり、このような透明導電膜である限り、とくに
限定はない。
[Examples] The transparent conductive film used in the present invention is a transparent conductive film having a thickness of about 0.01 to 1.0 μm that is generally used for manufacturing a semiconductor device. There is no limit.

該透明導電膜の具体例としては、ITO、ITO/SnO2、In
2O3、SnO2、Cdx Sn Oy(X=0.5〜2、Y=2〜4)、I
rz O1-z(z=0.33〜0.5)、CdOなどがあげられるが、
これらに限定されるものではない。
Specific examples of the transparent conductive film include ITO, ITO / SnO 2 , In
2 O 3 , SnO 2 , Cd x Sn Oy (X = 0.5 to 2, Y = 2 to 4), I
Examples include r z O 1-z (z = 0.33 to 0.5) and CdO.
It is not limited to these.

これらの導電膜はいずれも、水素原子を含んだような還
元性のプラズマにより還元されやすく、とくに温度が高
くなると一般的な化学反応のばあいと同様、その還元が
顕著におこる。
All of these conductive films are easily reduced by a reducing plasma containing hydrogen atoms, and the reduction is remarkable at a high temperature as in a general chemical reaction.

本発明において透明導電膜上に堆積される第1ドープ層
としては、たとえばa-Si:H、a-SiC:H、a-Ge:H、a-Si:F:
H、μc-Si:Hなどのp型あるいはn型のものが一般に用
いられるが、これらに限定されるものではない。
Examples of the first doped layer deposited on the transparent conductive film in the present invention include a-Si: H, a-SiC: H, a-Ge: H, and a-Si: F:
P-type or n-type ones such as H and μc-Si: H are generally used, but not limited to these.

第1ドープ層が堆積されたのちに形成される真性層およ
び第2ドープ層は、通常用いられる真性層および第1ド
ープ層と反対の導電タイプの第2ドープ層であれば、と
くに限定されるものではない。
The intrinsic layer and the second doped layer formed after the first doped layer is deposited are particularly limited as long as they are the second doped layer having a conductivity type opposite to that of the normally used intrinsic layer and the first doped layer. Not a thing.

このような真性層の具体例としては、a-Si:H、a-Si:F、
a-Si:F:H、a-SiGe:H、a-SiSn:H、a-SiN:Hなどのドープ
していないもの、あるいはBやPなどを微少量ドープし
たものなど、第2ドープ層の具体例としては、第1ドー
プ層がp型のばあいにはn型のμc-Si:H、a-SiC:H、a-S
i:H、a-SiN:Hなど、第1ドープ層がn型のばあいにはp
型のa-Si:H、μc-Si:H、a-SiC:Hなどがあげられる。
Specific examples of such an intrinsic layer include a-Si: H, a-Si: F,
Second doped layer, such as undoped ones such as a-Si: F: H, a-SiGe: H, a-SiSn: H, a-SiN: H, or those doped with a small amount of B or P As a specific example of, when the first doped layer is p-type, n-type μc-Si: H, a-SiC: H, aS
If the first doped layer is n-type, such as i: H and a-SiN: H, p
Examples include a-Si: H, μc-Si: H, and a-SiC: H.

本発明においては真性層の一部として堆積せしめられる
第1ドープ層に接する部分から80Åの厚さの部分までの
半導体層の堆積時の最高成膜温度が、そののち成膜され
る真性層の最高成膜温度より20〜250℃低い10〜180℃の
温度で成膜される。
In the present invention, the maximum film formation temperature at the time of deposition of the semiconductor layer from the part in contact with the first doped layer that is deposited as a part of the intrinsic layer to the part with a thickness of 80 Å is The film is formed at a temperature of 10 to 180 ° C, which is 20 to 250 ° C lower than the maximum film forming temperature.

本明細書にいう最高成膜温度とは、真性層の一部として
堆積せしめられる第1ドープ層に接する部分から80Åの
厚さの部分までの半導体層の部分においては、該部分の
半導体層を堆積する間での最も高い半導体層が堆積され
る表面の温度をいい、そののち成膜される真性層の部分
においては、該部分の成膜時の最も高い半導体層が堆積
される表面の温度をいう。
As used herein, the maximum film formation temperature means the semiconductor layer of a portion of the semiconductor layer from the portion in contact with the first doped layer deposited as a part of the intrinsic layer to the portion having a thickness of 80Å. The temperature of the surface on which the highest semiconductor layer is deposited during deposition, and in the part of the intrinsic layer that is subsequently formed, the highest temperature of the surface on which the semiconductor layer is deposited during film formation Say.

通常、透明導電膜の還元は第1ドープ層を形成するばあ
いに、とくに成膜温度が220℃程度あるいはこれ以上の
高温のばあいに顕著に生ずるが、第1ドープ層の厚さは
80〜300Å程度と薄いのが一般的であり、ばあいによっ
ては該層が島状に形成され島間にすきまが生じるため、
前記のごとき条件で真性層を形成する際にも、第1ドー
プ層を介して水素原子を含んだ還元性のプラズマにより
還元される。真性層堆積中には、さらに第1ドープ層の
ドーパント原子の拡散も進行する。
Usually, reduction of the transparent conductive film occurs remarkably when the first doped layer is formed, especially when the film forming temperature is about 220 ° C. or higher, but the thickness of the first doped layer is
It is generally as thin as about 80 to 300Å, and in some cases the layer is formed into islands and gaps occur between the islands.
Even when the intrinsic layer is formed under the above-mentioned conditions, it is reduced by the reducing plasma containing hydrogen atoms through the first doped layer. During the intrinsic layer deposition, diffusion of dopant atoms in the first doped layer also progresses.

しかし、真性層の一部として堆積せしめられる第1ドー
プ層に接する部分から80Åの厚さの部分まで、要すれば
80〜2000Åの厚さの部分までの半導体層の堆積時の最高
成膜温度が、そののち成膜される真性層の最高成膜温度
より20〜250℃低い温度、好ましくは10〜180℃の最高成
膜温度で成膜されると、成膜温度が低いため透明導電膜
が水素原子を含んだ還元性のプラズマと接触しても還元
されにくくなるとともに、第1ドープ層堆積時に還元し
て発生した金属や第1ドープ層中のドーパントの拡散も
防げる。したがって、生成する金属の量も少なくなると
ともに拡散も減少し、該金属による半導体層の汚染から
生ずる再結合中心の発生、ドーピング効率の低下などの
半導体特性の低下が著しい改善される。
However, from the part in contact with the first doped layer deposited as a part of the intrinsic layer to the part with a thickness of 80Å, if necessary,
The maximum film formation temperature during deposition of the semiconductor layer up to a thickness of 80 to 2000Å is 20 to 250 ° C lower than the maximum film formation temperature of the intrinsic layer to be formed thereafter, preferably 10 to 180 ° C. When the film is formed at the maximum film formation temperature, the film formation temperature is low, so that the transparent conductive film is less likely to be reduced even when contacted with a reducing plasma containing hydrogen atoms, and is reduced during the deposition of the first doped layer. It is also possible to prevent the generated metal and the diffusion of the dopant in the first doped layer. Therefore, the amount of metal produced is reduced and the diffusion is also reduced, and the deterioration of semiconductor characteristics such as the generation of recombination centers and the decrease of doping efficiency due to the contamination of the semiconductor layer by the metal is remarkably improved.

さらに第1ドープ層の最高成膜温度が10〜180℃で、第
1ドープ層に接する部分から80Åの厚さの部分まで、要
すれば80〜2000Åの厚さの部分までの半導体層の堆積時
の最高成膜温度と同じか、それより低くすることによ
り、上記透明導電膜が還元されにくくなるという効果が
より顕著にえられる。また、このような方法で成膜する
と、第1ドープ層、第1ドープ層に接する部分から80Å
の厚さの部分まで、要すれば80〜2000Åの厚さの部分ま
での半導体層、そののち成膜される真性層の部分を低い
成膜温度から高い成膜温度へ階段的に成膜温度を上げて
成膜することができるので、内部応力の小さいp層、内
部応力の大きい真性層の間が円滑につながり、酸化物透
明導電膜/第1ドープ層/第1ドープ層に接する部分か
ら80Åの厚さの部分まで、要すれば80〜2000Åの厚さの
部分までの半導体層/そののち成膜される真性層の各界
面における力学的なストレスに起因するダングリングボ
ンドなどの欠陥の発生を減少させることができる。さら
には、第1ドープ層/第1ドープ層に接する部分から80
Åの厚さの部分まで、要すれば80〜2000Åの厚さの部分
までの半導体層/そののち成膜される半導体層の各層の
禁止帯幅が、広いものから狭いものへスムーズに変化す
るため、該界面の内部電界を従来の第1ドープ層/真性
層の界面に比べて均一に大きくすることができる。また
該第1ドープ層をa-SiC:Hなどの禁止帯幅の広い材料に
することにより、内部電界をさらに大きくすることがで
きる。さらに第1ドープ層がμc-Si:H層のばあいには、
μc:Si:Hと真性との間の界面の円滑なものがえられると
いう効果がえられる。
Furthermore, the maximum film forming temperature of the first doped layer is 10 to 180 ° C, and the semiconductor layer is deposited from the portion in contact with the first doped layer to the portion with a thickness of 80 Å, if necessary, to the portion with a thickness of 80 to 2000 Å. By setting the temperature equal to or lower than the maximum film forming temperature at that time, the effect that the transparent conductive film is less likely to be reduced can be more remarkable. In addition, when the film is formed by such a method, 80 Å from the first doped layer and the part in contact with the first doped layer
Thickness of the semiconductor layer up to the thickness of 80 to 2000Å, and the intrinsic layer to be deposited after that, from the low deposition temperature to the high deposition temperature. Since the p-layer having a small internal stress and the intrinsic layer having a large internal stress are smoothly connected to each other, it is possible to form a film by raising Defects such as dangling bonds due to mechanical stress at the interfaces of the semiconductor layer / intrinsic layer that is subsequently deposited up to the thickness of 80 Å, if necessary, up to the thickness of 80 to 2000 Å Occurrence can be reduced. Further, from the first doped layer / portion in contact with the first doped layer, 80
The forbidden band width of the semiconductor layer up to the thickness of Å, if necessary, up to the thickness of 80 to 2000 Å / semiconductor layers to be subsequently formed, changes smoothly from wide to narrow Therefore, the internal electric field at the interface can be uniformly increased as compared with the conventional first doped layer / intrinsic layer interface. The internal electric field can be further increased by using a material having a wide band gap such as a-SiC: H for the first doped layer. Furthermore, when the first doped layer is a μc-Si: H layer,
The effect is that a smooth interface between μc: Si: H and intrinsic can be obtained.

前記第1ドープ層に接する部分から80Åの厚さの部分ま
で、要すれば80〜2000Åの厚さの部分までの半導体層
(低い最高成膜温度で成膜される真性層)を成膜するば
あいのプラズマ条件は、たとえば圧力を0.2〜2.5Torrの
範囲で、グロー放電を維持可能な最大またはその近傍の
圧力にすることが好ましく、RFパワーはグロー放電を維
持可能な範囲(5〜20mW/cm2)で最小になるようにする
のが好ましく、このようにすることにより、そののち成
膜される真性層の最高成膜温度より20〜250℃低い10〜1
80℃の最高成膜温度でも光導電率のσphを10-5(Ωcm)
-1以上にすることができ、光学的禁止帯幅Eoptを1.8eV
程度にすることができる。また、透明導電膜に対するプ
ラズマの影響も小さくできる。
A semiconductor layer (intrinsic layer formed at a low maximum film formation temperature) is formed from a portion in contact with the first doped layer to a portion having a thickness of 80Å, and if necessary, a portion having a thickness of 80 to 2000Å In this case, it is preferable that the plasma condition is, for example, a pressure in the range of 0.2 to 2.5 Torr, and a pressure at or near the maximum at which the glow discharge can be maintained, and the RF power is in the range (5 to 20 mW / cm 2 ), which is preferably 10 to 1 ° C., which is 20 to 250 ° C. lower than the maximum film formation temperature of the subsequently formed intrinsic layer.
Photoconductivity σ ph of 10 -5 (Ωcm) even at the maximum film forming temperature of 80 ° C
-1 or more, optical bandgap E opt 1.8eV
It can be a degree. Further, the influence of plasma on the transparent conductive film can be reduced.

しかしながら、この低い最高成膜温度で成膜した真性層
の電気的特性は、高い最高成膜温度で作製される真性層
の特性に較べて劣るばあいもあるので、真性層全体を低
い最高成膜温度で作製するのは好ましくなく、実用上は
通常の真性層を作る際にプラズマの影響を少なくでき、
透明導電膜の変質および第1ドープ層中のドーパントの
拡散を防ぐことができる厚さだけ、低い最高成膜温度で
真性層を堆積させればよい。すなわち、低い最高成膜温
度の真性層の成膜条件によって第1ドープ層に接する部
分から80Åの厚さの部分まで、要すれば80〜2000Åの厚
さの部分まで、真性層の一部を堆積させることで本発明
の効果がえられる。
However, since the electrical properties of the intrinsic layer formed at this low maximum film forming temperature may be inferior to those of the intrinsic layer formed at the high maximum film forming temperature, the entire intrinsic layer may have a low maximum film forming temperature. It is not preferable to make it at the film temperature, and in practice it is possible to reduce the influence of plasma when making a normal intrinsic layer,
The intrinsic layer may be deposited at a low maximum film forming temperature by a thickness that can prevent alteration of the transparent conductive film and diffusion of the dopant in the first doped layer. That is, depending on the film formation conditions of the intrinsic layer having a low maximum film formation temperature, a part of the intrinsic layer is contacted from the part in contact with the first doped layer to the part having a thickness of 80 Å, if necessary, to the part having a thickness of 80 to 2000 Å. The effect of the present invention can be obtained by depositing.

もちろん低い最高成膜温度で堆積する真性層の厚さが、
たとえば500Å、1000Åさらには2000Åと大きくなると
透明導電膜の還元あるいは金属の拡散を防止するという
効果は大きくなるが、上記のような理由であまり大きい
値は好ましくない。低い最高成膜温度で堆積する真性層
の好ましい厚さは150〜400Åであり、最も好ましい厚さ
は200〜300Åである。
Of course, the thickness of the intrinsic layer deposited at a low maximum deposition temperature is
For example, if it becomes as large as 500Å, 1000Å, or even 2000Å, the effect of preventing reduction of the transparent conductive film or diffusion of metal becomes great, but a too large value is not preferable for the above reasons. The preferred thickness of the intrinsic layer deposited at low maximum deposition temperature is 150-400Å, the most preferred thickness is 200-300Å.

低い最高成膜温度で成膜される真性層の成膜温度は一定
である必要はなく、徐々に変化させてもよい。要はその
のち成膜される半導体層の最高成膜温度より少なくとも
第1ドープ層に接する部分から80Åの厚さの部分まで、
要すれば80〜2000Åの厚さの部分までの成膜が20〜250
℃、好ましくは50〜200℃低い最高成膜温度で行なわれ
ればよいのである。
The film formation temperature of the intrinsic layer formed at a low maximum film formation temperature does not have to be constant, and may be gradually changed. The point is that, from the maximum film formation temperature of the semiconductor layer to be formed thereafter, at least from the portion in contact with the first doped layer to the portion having a thickness of 80 Å,
If necessary, film deposition up to 80-2000Å thickness is 20-250
It may be carried out at a maximum film forming temperature which is lower by 50 ° C., preferably 50 to 200 ° C.

なお低い最高成膜温度で成膜される真性層の堆積時にお
ける透明導電膜へのプラズマの影響をさけるには、最高
成膜温度10〜180℃で堆積するのが好ましい。
In order to avoid the influence of plasma on the transparent conductive film during the deposition of the intrinsic layer formed at a low maximum film forming temperature, it is preferable to deposit at the maximum film forming temperature of 10 to 180 ° C.

本発明の方法を実施するための装置としては、通常の容
量結合型RF平行平板型CVD装置、誘導結合型RFCVD装置、
DC平行平板型CVD装置などがあげられるが、これらに限
定されるものではない。とくに平行平板型CVD装置にお
いて顕著な効果がみられる。
As an apparatus for carrying out the method of the present invention, a normal capacitive coupling type RF parallel plate type CVD apparatus, an inductive coupling type RFCVD apparatus,
Examples of the DC parallel plate type CVD device include, but are not limited to. In particular, a remarkable effect is seen in the parallel plate type CVD apparatus.

つぎに本発明の方法を実施例に基づき説明する。Next, the method of the present invention will be described based on examples.

実施例1および比較例1 ガラス板上に、スプレー法にて厚さ4000ÅのSnO2電極を
形成し、これを基板として用いた。
Example 1 and Comparative Example 1 A 4000 Å-thick SnO 2 electrode was formed on a glass plate by a spray method, and this was used as a substrate.

該基板上に、基板温度30℃、CVD圧力1.5Torr、SiH4/CH
4の流量比が2/3、SiH4+CH4の合計流量に対してB2H6
正味流量が1%になるようにして、RFパワー密度10mW/c
m2でp型a-SiC:H層を100Å堆積させたのち、成膜温度10
0℃(一定)、CVD圧力1TorrでSiH4ガスを用いてRFパワ
ー密度10mW/cm2でi型a-Si:H層(低い最高成膜温度で成
膜した真性層)を200Å堆積させた。ついで成膜温度190
℃(一定)、CVD圧力1.0TorrでSiH4ガスを用い、10mW/c
m2でi型a-Si:H層を6000Å堆積させた。さらに成膜温度
180℃(一定)、CVD圧力2TorrでSiH4に対しPH3が1流量
%、H2が30流量倍になるように導入し、RFパワー密度70
mW/cm2でn型μc-Si:H層を300Å堆積させ、電極としてA
lを真空蒸着法により1000Å堆積させて、1cm2の面積を
有する太陽電池を作製した。
On the substrate, the substrate temperature is 30 ° C, the CVD pressure is 1.5 Torr, and SiH 4 / CH.
The RF power density is 10 mW / c with the flow rate ratio of 4 is 2/3 and the net flow rate of B 2 H 6 is 1% with respect to the total flow rate of SiH 4 + CH 4.
After depositing 100 Å p-type a-SiC: H layer at m 2 , the deposition temperature is 10
200 Å of i-type a-Si: H layer (intrinsic layer formed at low maximum film forming temperature) was deposited at 0 ° C (constant) and CVD pressure of 1 Torr using SiH 4 gas with RF power density of 10 mW / cm 2 . . Then the film formation temperature 190
℃ (constant), CVD pressure 1.0 Torr, SiH 4 gas, 10mW / c
An i-type a-Si: H layer was deposited at 6000Å in m 2 . Further film formation temperature
180 ° C. (constant), PH 3 1 flow rate% relative to SiH 4 in CVD pressure 2 Torr, introducing as H 2 is 30 flow rate doubled, RF power density 70
n-type μc-Si: H layer was deposited 300 Å at mW / cm 2
l was deposited by a vacuum vapor deposition method to 1000 L to prepare a solar cell having an area of 1 cm 2 .

えられた太陽電池の特性をAM-1、100mW/cm2のソーラー
シュミレーターを用いて測定すると、JSC15.2mA、VOC0.
9V、FF 61.0%、η 8.4%であった。またえられた太陽
電池の電流電圧特性を測定した結果を第1図に示す。
The characteristics of the obtained solar cell were measured using AM-1, 100mW / cm 2 solar simulator, J SC 15.2mA, V OC 0.
It was 9V, FF 61.0%, and η 8.4%. Moreover, the result of having measured the current-voltage characteristic of the obtained solar cell is shown in FIG.

また比較用試料として、成膜温度100℃(一定)で成膜
したi型a-Si:H層を堆積しない以外は実施例1と同様に
して太陽電池を作製し、太陽電池の特性を測定すると、
JSC15.0mA、VOC0.78V、FF 59.5%、η 6.96%であっ
た。またえられた太陽電池の電流電圧特性を測定した結
果を第1図に示す。
As a comparative sample, a solar cell was prepared in the same manner as in Example 1 except that the i-type a-Si: H layer formed at the film formation temperature of 100 ° C. (constant) was not deposited, and the characteristics of the solar cell were measured. Then,
It was J SC 15.0mA, V OC 0.78V, FF 59.5%, and η 6.96%. Moreover, the result of having measured the current-voltage characteristic of the obtained solar cell is shown in FIG.

なお成膜温度の測定は、半導体層が堆積される基板表面
にプラズマ電解の影響を受けないことを確認した極細の
クロメル・アロメル熱電対をとりつけて行なった。
The film-forming temperature was measured by mounting an ultrafine chromel-alomer thermocouple on the surface of the substrate on which the semiconductor layer was deposited, which was confirmed not to be affected by plasma electrolysis.

[発明の効果] 本発明の方法により半導体装置を製造すると、VOC、F
F、ηが著しく改善された半導体装置がえられる。
[Effects of the Invention] When a semiconductor device is manufactured by the method of the present invention, V OC , F
A semiconductor device having significantly improved F and η can be obtained.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明の方法および従来法により製造された半
導体装置(太陽電池)の電流電圧特性を示すグラフであ
る。
FIG. 1 is a graph showing current-voltage characteristics of a semiconductor device (solar cell) manufactured by the method of the present invention and the conventional method.

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】透明導電膜上に非晶質半導体を第1不純物
ドープ層、真性層、第1不純物ドープ層と反対の導電タ
イプの第2不純物ドープ層の順に堆積する際に、真性層
の一部として堆積せしめられる第1不純物ドープ層に接
する部分から80Åの厚さの部分までの半導体層の堆積時
の最高成膜温度が、そののち成膜される真性層の最高成
膜温度より20〜250℃低い10〜180℃で成膜されることを
特徴とする半導体装置の製造方法。
1. When depositing an amorphous semiconductor on a transparent conductive film in the order of a first impurity-doped layer, an intrinsic layer, and a second impurity-doped layer of a conductivity type opposite to that of the first impurity-doped layer, The maximum deposition temperature of the semiconductor layer from the portion in contact with the first impurity-doped layer that is deposited as a part to the portion with a thickness of 80 Å is 20 times higher than the maximum deposition temperature of the intrinsic layer to be deposited thereafter. A method for manufacturing a semiconductor device, characterized in that the film is formed at 10 to 180 ° C. lower by 250 ° C.
【請求項2】第1不純物ドープ層の最高成膜温度が10〜
180℃で、前記第1不純物ドープ層に接する部分から80
Åの厚さまでの真性層の最高成膜温度と同等以下である
特許請求の範囲第1項記載の製造方法。
2. The maximum film formation temperature of the first impurity-doped layer is 10 to 10.
80 ° C from the portion in contact with the first impurity-doped layer to 80 ° C
The manufacturing method according to claim 1, which is equal to or lower than the maximum film formation temperature of the intrinsic layer up to the thickness of Å.
【請求項3】第1不純物ドープ層がa-SiC:H層またはμc
-Si:H層である特許請求の範囲第1項記載の製造方法。
3. The first impurity-doped layer is an a-SiC: H layer or μc
-The manufacturing method according to claim 1, which is a Si: H layer.
JP60091736A 1985-04-26 1985-04-26 Method for manufacturing semiconductor device Expired - Lifetime JPH071752B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60091736A JPH071752B2 (en) 1985-04-26 1985-04-26 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60091736A JPH071752B2 (en) 1985-04-26 1985-04-26 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPS61251020A JPS61251020A (en) 1986-11-08
JPH071752B2 true JPH071752B2 (en) 1995-01-11

Family

ID=14034801

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60091736A Expired - Lifetime JPH071752B2 (en) 1985-04-26 1985-04-26 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JPH071752B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6566594B2 (en) 2000-04-05 2003-05-20 Tdk Corporation Photovoltaic element

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57157577A (en) * 1981-03-23 1982-09-29 Sumitomo Electric Ind Ltd Manufacture of thin film photovoltaic element

Also Published As

Publication number Publication date
JPS61251020A (en) 1986-11-08

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