JPH0562830B2 - - Google Patents
Info
- Publication number
- JPH0562830B2 JPH0562830B2 JP60242288A JP24228885A JPH0562830B2 JP H0562830 B2 JPH0562830 B2 JP H0562830B2 JP 60242288 A JP60242288 A JP 60242288A JP 24228885 A JP24228885 A JP 24228885A JP H0562830 B2 JPH0562830 B2 JP H0562830B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- intrinsic layer
- intrinsic
- film
- temperature
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000000151 deposition Methods 0.000 claims description 37
- 230000008021 deposition Effects 0.000 claims description 28
- 239000004065 semiconductor Substances 0.000 claims description 23
- 230000015572 biosynthetic process Effects 0.000 claims description 13
- 238000000034 method Methods 0.000 claims description 13
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 12
- 239000012535 impurity Substances 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 229910021424 microcrystalline silicon Inorganic materials 0.000 claims description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims 1
- 229910010271 silicon carbide Inorganic materials 0.000 claims 1
- 230000000694 effects Effects 0.000 description 6
- 239000007789 gas Substances 0.000 description 6
- 230000001603 reducing effect Effects 0.000 description 6
- 239000000758 substrate Substances 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 5
- 239000002019 doping agent Substances 0.000 description 5
- 230000006866 deterioration Effects 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 4
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 3
- 229910017875 a-SiN Inorganic materials 0.000 description 3
- 230000000052 comparative effect Effects 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 229910006404 SnO 2 Inorganic materials 0.000 description 2
- 229910006852 SnOy Inorganic materials 0.000 description 2
- 125000004429 atom Chemical group 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 229910021419 crystalline silicon Inorganic materials 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 125000004435 hydrogen atom Chemical group [H]* 0.000 description 2
- 230000006798 recombination Effects 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910020328 SiSn Inorganic materials 0.000 description 1
- 229910017817 a-Ge Inorganic materials 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(III) oxide Inorganic materials [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000001782 photodegradation Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
Landscapes
- Photovoltaic Devices (AREA)
Description
【発明の詳細な説明】
「産業上の利用分野」
本発明は半導体装置の製造方法に関し、更に詳
しくは製造時間を大巾に短縮でき、かつVoc，
Jsc，F.F.，ηが著しく改善された半導体装置を
製造する方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to a method for manufacturing a semiconductor device, and more specifically, the present invention relates to a method for manufacturing a semiconductor device.
The present invention relates to a method for manufacturing a semiconductor device with significantly improved Jsc, FF, and η.
「従来の技術」
非晶質半導体層を含む太陽電池などの半導体装
置の材料としてａ−Si：Ｈ、ａ−SiC：Ｈ、ａ−
SiGe：Ｈ、ａ−SiN：Ｈ、ａ−Si：Ｆ：Ｈ、ａ−
Ge：Ｈなどや、これらの微結晶半導体などが用
いられている。これらの成膜はRFまたはDCのプ
ラズマCVD装置を用いて行うのが通常である。"Prior art" As materials for semiconductor devices such as solar cells containing amorphous semiconductor layers, a-Si:H, a-SiC:H, a-
SiGe:H, a-SiN:H, a-Si:F:H, a-
Ge:H and these microcrystalline semiconductors are used. These films are usually formed using an RF or DC plasma CVD device.
従来法では、この種の装置を用いて220℃前後
以上の成膜温度ですべての非晶質半導体層を堆積
させている。また成膜時間の短縮の為に、10Å／
秒以上で真性層を高速成膜しているが、このとき
の成膜速度、成膜温度は真性層全体において一定
である。 In the conventional method, all amorphous semiconductor layers are deposited using this type of equipment at a deposition temperature of around 220°C or higher. In addition, in order to shorten the film formation time,
Although the intrinsic layer is formed at high speed in seconds or more, the film forming speed and film forming temperature at this time are constant over the entire intrinsic layer.
「発明が解決しようとする問題点」
このような方法で成膜するとプラズマ中の電子
や、半導体形成ガスの分解生成物であるイオンや
カジカルなどが基板面に直接衝突するため、
ITO、In2O3、ITO／SnO2、CdxSnOy（ｘ＝0.5〜
２、ｙ＝２〜４）：IrzO1-z（ｚ＝0.33〜0.5）など
から形成された透明導電膜が、一部または全体に
わたつて還元され金属化する。``Problems to be solved by the invention'' When a film is formed using this method, electrons in the plasma and ions and radicals that are decomposition products of the semiconductor forming gas directly collide with the substrate surface.
ITO, In 2 O 3 , ITO/SnO 2 , Cd x SnOy (x=0.5~
2, y=2-4): A transparent conductive film formed from IrzO 1-z (z=0.33-0.5) or the like is partially or entirely reduced and metallized.
この現象は第１不純物ドープ層堆積後の真性層
の堆積プロセスにおいても、成膜温度が220℃前
後の場合には第１不純物ドープ層のすき間を通し
て、電子やイオンやラジカルなどが基板面に衝突
するため生ずる。とくに、高速成膜の場合、プラ
ズマの還元性が高くなるので、この効果は顕著で
ある。 This phenomenon occurs even during the deposition process of the intrinsic layer after the deposition of the first impurity doped layer, when the film formation temperature is around 220°C, electrons, ions, radicals, etc. collide with the substrate surface through the gaps in the first impurity doped layer. arise because of In particular, in the case of high-speed film formation, this effect is remarkable because the reducing property of the plasma becomes high.
このようにして生成した金属は、堆積された第
１不純物ドープ層のみならず真性層にまで拡散し
て、一種のドーパントとして作用したり、真性層
で発生した電子やホールを打消してしまう再結合
中心になつたりするため、半導体／透明導電膜の
界面や第１不純物ドープ層／真性層の界面が著し
く劣化する。 The metal produced in this way diffuses not only into the deposited first impurity doped layer but also into the intrinsic layer, acting as a kind of dopant, or by canceling the electrons and holes generated in the intrinsic layer. Because it becomes a bonding center, the semiconductor/transparent conductive film interface and the first impurity doped layer/intrinsic layer interface are significantly deteriorated.
この拡散は、第１不純物ドープ層の堆積中のみ
ならず真性層堆積中にも進行するが、真性層堆積
中にはさらに第１不純物ドープ層のドーパント原
子の拡散も進行する。 This diffusion proceeds not only during the deposition of the first impurity-doped layer but also during the deposition of the intrinsic layer, and the diffusion of the dopant atoms of the first impurity-doped layer also proceeds during the deposition of the intrinsic layer.
さらに前記金属化が生じると、透明導電膜その
ものの導電性や透明性も低下するため、半導体装
置の特性、とくに光電変換特性が大巾に低下す
る。 Furthermore, when the metallization occurs, the conductivity and transparency of the transparent conductive film itself decreases, and therefore the characteristics of the semiconductor device, particularly the photoelectric conversion characteristics, decrease significantly.
本発明は半導体層堆積のプロセスの時間短縮を
図るために高速成膜する場合に於いて、前記のご
とき透明導電膜上に非晶質半導体を堆積する際に
おこる透明導電膜の変質により生ずる問題を少な
くしようとするものであり、さらに第２不純物ド
ープ層と真性層との間の内蔵電界を強めることに
より前記再結合中心の影響を低減せんとするもの
である。 The present invention addresses the problems that occur due to deterioration of the transparent conductive film that occurs when depositing an amorphous semiconductor on the transparent conductive film as described above, in the case of high-speed film formation in order to shorten the process time of semiconductor layer deposition. The purpose is to reduce the influence of the recombination center by strengthening the built-in electric field between the second impurity doped layer and the intrinsic layer.
「問題点を解決するための手段」
本発明は透明導電膜上に非晶質半導体を第１不
純物ドープ層（以下、第１ドープ層という）、真
性層、第１ドープ層と反対の導電タイプの第２不
純物ドープ層（以下、第２ドープ層という）の順
に堆積するプロセスに於いて、真性層の第１ドー
プ層側の厚さ80〜1000Åの部分（以下、第１真性
層という）の堆積速度を４Å／秒以下、好ましく
は0.5〜４Å／秒とし、残りの真性層の部分（以
下、第２真性層という）の積進速度を６Å／秒以
上、好ましくは６〜80Å／秒とし、かつ第１真性
層の成膜温度の最高値が10〜100℃であり且つ第
２真性層の成膜温度の最高値より20〜250℃低く
することを特徴とする半導体装置の製造方法を内
容とするものである。"Means for Solving the Problems" The present invention provides a first impurity doped layer (hereinafter referred to as the first doped layer), an intrinsic layer, and a conductivity type opposite to the first doped layer. In the process of sequentially depositing the second impurity doped layer (hereinafter referred to as the second doped layer), a portion of the intrinsic layer with a thickness of 80 to 1000 Å on the first doped layer side (hereinafter referred to as the first intrinsic layer) is The deposition rate is 4 Å/sec or less, preferably 0.5 to 4 Å/sec, and the deposition rate of the remaining intrinsic layer portion (hereinafter referred to as the second intrinsic layer) is 6 Å/sec or more, preferably 6 to 80 Å/sec. , and the maximum value of the film formation temperature of the first intrinsic layer is 10 to 100 °C and is 20 to 250 °C lower than the maximum value of the film formation temperature of the second intrinsic layer. The content shall be as follows.
本発明に用いる透明電導膜とは、半導体装置の
製造に一般に使用される厚さ0.01〜1.0μm程度の
透明導電膜のことであり、このような透明導電膜
である限り、とくに限定はない。 The transparent conductive film used in the present invention is a transparent conductive film with a thickness of about 0.01 to 1.0 μm that is generally used in the manufacture of semiconductor devices, and is not particularly limited as long as it is such a transparent conductive film.
該透明導電膜の具体例としては、ITO、ITO／
SnO2、In2O3、SnO2、CdxSnOy（ｘ＝0.5〜２、ｙ
＝２〜４）、IrzO1-z（ｚ＝0.33〜0.5）CdOなどが
あげられるが、これらに限定されるものではな
い。 Specific examples of the transparent conductive film include ITO, ITO/
SnO2 , In2O3 , SnO2 , Cd x SnOy ( x =0.5~2, y
=2-4), IrzO1 -z (z=0.33-0.5), CdO, etc., but are not limited to these.
これらの導電膜はいずれも、水素電子を含んだ
ような還元性のプラズマにより還元されやすく、
とくに温度が高くなると一般的な化学反応の場合
と同様、その還元が顕著におこる。 All of these conductive films are easily reduced by reducing plasma containing hydrogen electrons.
In particular, when the temperature becomes high, reduction occurs significantly, as in the case of general chemical reactions.
本発明において透明導電膜上に堆積される第１
ドープ層としては、たとえばａ−Si：Ｈ、ａ−
SiC：Ｈ、ａ−Ge：Ｈ、ａ−Si：Ｆ：Ｈ、μc−
Si：ＨなどのＰ型あるいはｎ型のものが一般に用
いられるが、これらに限定されるものではない。 In the present invention, the first layer deposited on the transparent conductive film
As the doped layer, for example, a-Si:H, a-
SiC:H, a-Ge:H, a-Si:F:H, μc-
P-type or n-type materials such as Si:H are generally used, but are not limited to these.
第１ドープ層が堆積された後に形成される真性
層及び第２ドープ層は、通常用いられる真性層お
よび第１ドープ層と反対の導電タイプの第２ドー
プ層であれば、とくに限定されるものではない。 The intrinsic layer and the second doped layer formed after the first doped layer are deposited are particularly limited, provided that the second doped layer is of the opposite conductivity type as the normally used intrinsic layer and the first doped layer. isn't it.
このような真性層の具体例としては、ａ−Si：
Ｈ、ａ−Si：Ｆ、ａ−Si：Ｆ：Ｈ、ａ−SiGe：
Ｈ、ａ−SiSn：Ｈ、ａ−SiN：Ｈなどのドープし
てないもの、あるいはＢやＰなどを微少量ドープ
したものなど、第２ドープ層の具体例としては、
第１ドープ層がＰ型の場合にはｎ型のμc−Si：
Ｈ、ａ−SiC：Ｈ、ａ−Si：Ｈ、ａ−SiN：Ｈな
ど、第１ドープ層がｎ型のばあいにはＰ型のａ−
Si：Ｈ、μc−Si：Ｈ、ａ−SiC：Ｈなどがあげら
れる。 Specific examples of such intrinsic layers include a-Si:
H, a-Si:F, a-Si:F:H, a-SiGe:
Specific examples of the second doped layer include undoped layers such as H, a-SiSn:H, and a-SiN:H, or those doped with a small amount of B, P, etc.
When the first doped layer is P-type, n-type μc-Si:
H, a-SiC:H, a-Si:H, a-SiN:H, etc., when the first doped layer is n-type, P-type a-
Examples include Si:H, μc-Si:H, and a-SiC:H.
本発明において、前記第１真性層は成膜速度が
４Å／秒以下で、且つ第２真性層の成膜温度の最
高値より20〜250℃低い温度で成膜される。 In the present invention, the first intrinsic layer is deposited at a deposition rate of 4 Å/sec or less and at a temperature 20 to 250° C. lower than the maximum deposition temperature of the second intrinsic layer.
通常、透明導電膜の還元は第１ドープ層を堆積
した後には、該ドープ層がプラズマ中の電子やイ
オンやラジカルの基板面への衝突から透明導電膜
を保護するので少なくなる。しかし第１ドープ層
の厚さは80〜300Å程度と薄く、場合によつては
該膜が島状に形成されるため、前記のごとき条件
で真性層を形成する際にも、第１ドープ層を介し
て水素原子を含んだ還元性のプラズマにより透明
導電膜は還元される。 Normally, reduction of the transparent conductive film is reduced after depositing the first doped layer because the doped layer protects the transparent conductive film from bombardment of the substrate surface by electrons, ions, and radicals in the plasma. However, the thickness of the first doped layer is as thin as about 80 to 300 Å, and in some cases the film is formed like an island, so even when forming an intrinsic layer under the above conditions, the first doped layer The transparent conductive film is reduced by the reducing plasma containing hydrogen atoms via the .
さらに高速で膜堆積をする場合においては、使
用ガスの流量を増加し、成膜温度を高めてRF電
力を増加させる必要があるため、プラズマの還元
性はより顕著になる。 When depositing a film at an even higher speed, it is necessary to increase the flow rate of the gas used, raise the film-forming temperature, and increase the RF power, so the reducing nature of the plasma becomes more pronounced.
真性層堆積中には、さらに第１ドープ層のドー
パント原子の拡散も進行する。 During the deposition of the intrinsic layer, the dopant atoms of the first doped layer also diffuse.
しかし、本発明のように第１真性層、即ち、第
ドープ層に接する厚さ80〜1000Å好ましくは100
〜500Åの真性層の部分の堆積速度を４Å／秒以
下とし、そののち成膜される真性層の部分（第２
真性層）の堆積速度を６Å／秒以上、好ましくは
10Å／秒以上にし、第１真性層の成膜温度の最高
値を第２真性層の成膜温度の最高値より20〜250
℃低い温度、好ましくは１〜100℃にすると、第
１真性層の堆積時の還元性が小さいために、透明
電導膜が水素原子を含んだ還元性のプラズマと接
触しても還元されにくくなるとともに、第１ドー
プ層堆積時に還元して発生した金属や第１ドープ
層中のドーパントの拡散も防げる。従つて、生成
する金属の量も少なくなるとともに拡散も減少
し、該金属による半導体層の汚染から生ずる再結
合中心の発生、ドーピング効率の低下などの半導
体特性の低下が著しく改善される。 However, as in the present invention, the thickness of the first intrinsic layer, that is, the thickness in contact with the first doped layer is 80 to 1000 Å, preferably 100 Å.
The deposition rate of the ~500 Å intrinsic layer portion is set to 4 Å/sec or less, and then the intrinsic layer portion (second
(intrinsic layer) deposition rate of 6 Å/sec or more, preferably
10 Å/sec or more, and the maximum value of the film-forming temperature of the first intrinsic layer is 20 to 250 degrees higher than the maximum value of the film-forming temperature of the second intrinsic layer.
When the temperature is low, preferably 1 to 100°C, the reducing property of the first intrinsic layer during deposition is low, so that the transparent conductive film becomes difficult to be reduced even if it comes into contact with reducing plasma containing hydrogen atoms. At the same time, it is also possible to prevent diffusion of the metal generated by reduction during deposition of the first doped layer and the dopant in the first doped layer. Therefore, the amount of metal produced is reduced and the diffusion is also reduced, and deterioration in semiconductor properties such as generation of recombination centers and deterioration of doping efficiency resulting from contamination of the semiconductor layer by the metal is significantly improved.
さらに第１ドープ層の成膜温度の最高値が10〜
100℃で、第１真性層の成膜温度と同じか、それ
より低くすることにより上記透明導電膜が還元さ
れにくくなるという効果がより顕著に得られる。 Furthermore, the maximum value of the film formation temperature of the first doped layer is 10~
By setting the temperature to 100° C., which is the same as or lower than the film-forming temperature of the first intrinsic layer, the effect that the transparent conductive film is less likely to be reduced can be more prominently obtained.
また、このような方法で成膜すると、第１ドー
プ層、第１真性層、そののち成膜される半導体の
部分を低い成膜温度から高い成膜温度へ階段的に
成膜温度を上げて成膜することができるので、内
部応力の小さいＰ層、内部応力の大きい真性層の
間が円滑につながり酸化物透明導電膜／第１ドー
プ層／第１真性層／そののち成膜される半導体層
の各界面における力学的なストレスが緩和され、
このストレスに起因する光劣化効果を少なくする
ことができる。 In addition, when forming a film using this method, the film forming temperature is increased stepwise from a low film forming temperature to a high film forming temperature for the first doped layer, the first intrinsic layer, and the semiconductor portion that will be formed later. Because it can be formed into a film, the P layer with low internal stress and the intrinsic layer with high internal stress are smoothly connected to each other. The mechanical stress at each interface of the layers is alleviated,
The photodegradation effect caused by this stress can be reduced.
さらには、第１ドープ層／第１真性層／そのの
ち成膜される半導体層の各層の禁止帯幅が広いも
のから狭いものへスムーズに変化するため、該界
面の内部電界を従来の第１ドープ層、真性層の界
面に比べて均一に大きくすることができる。また
該第１ドープ層をａ−SiC：Ｈなどの禁止帯幅の
広い材料にすることにより、内部電界をさらに大
きくすることができる。さらに第１ドープ層が
μc−Si：Ｈ層のばあいには、μc−Si：Ｈと真性と
の間の界面の円滑なものが得られるという効果が
えられる。 Furthermore, since the forbidden band width of each layer of the first doped layer/first intrinsic layer/semiconductor layer formed after that changes smoothly from wide to narrow, the internal electric field at the interface can be reduced compared to the conventional first doped layer. It can be made uniformly larger than the interface between the doped layer and the intrinsic layer. Furthermore, by using a material with a wide forbidden band width, such as a-SiC:H, for the first doped layer, the internal electric field can be further increased. Furthermore, when the first doped layer is a .mu.c-Si:H layer, it is possible to obtain a smooth interface between .mu.c-Si:H and the intrinsic layer.
前記、第１真性層を成膜する条件は、たとえば
圧力を0.2〜2.5Torrの範囲で、グロー放電を維持
可能な最大またはその近傍の圧力にすることが好
ましく、RFパワーはグロー放電を維持可能な範
囲（５〜20mW／cm2）で最小になるようにするの
が好ましく、このようにすることにより、真性層
よりあとの半導体層の成膜温度より20〜250℃低
い成膜温度でも光導電率σphを10-5（Ωcm）-1以上
にすることができ、光学的禁止帯幅Eoptを1.8ev
程度にすることができる。また、透明導電膜に対
するプラズマの影響も小さくできる。 The conditions for forming the first intrinsic layer are, for example, a pressure in the range of 0.2 to 2.5 Torr, preferably at or near the maximum pressure that can maintain glow discharge, and RF power that can maintain glow discharge. It is preferable to minimize the power in the range (5 to 20 mW/cm 2 ), and by doing so, the light can be maintained even at a film formation temperature that is 20 to 250 degrees Celsius lower than the film formation temperature of the semiconductor layer after the intrinsic layer. Conductivity σph can be increased to 10 -5 (Ωcm) -1 or higher, and optical bandgap Eopt can be reduced to 1.8ev.
It can be done to a certain extent. Furthermore, the influence of plasma on the transparent conductive film can also be reduced.
しかしながら、この低い成膜温度で成膜した、
第１真性層の電気的特性は、通常の成膜条件で得
られる真性層の特性、もしくは前記第２真性層の
特性に較べて劣る場合もあるので、この層を厚く
するのは好ましくなく、実用上は第２真性層を堆
積する際の高速成膜条件のプラズマの影響を少な
くでき、透明導電膜の変質および第１ドープ層中
のドーパントの拡散を防ぐことができる厚さだ
け、この第１真性層を堆積すればよい。すなわ
ち、第１真性層を80Å以上好ましくは250Å前後
の厚さで堆積させることで効果が得られる。 However, the film formed at this low film-forming temperature,
The electrical characteristics of the first intrinsic layer may be inferior to the characteristics of the intrinsic layer obtained under normal film formation conditions or the characteristics of the second intrinsic layer, so it is not preferable to make this layer thick. In practice, the thickness of this second intrinsic layer is such that it can reduce the influence of plasma under high-speed deposition conditions when depositing the second intrinsic layer, and prevent deterioration of the transparent conductive film and diffusion of dopants in the first doped layer. One intrinsic layer may be deposited. That is, the effect can be obtained by depositing the first intrinsic layer to a thickness of 80 Å or more, preferably about 250 Å.
第１真性層の堆積速度、成膜温度は一定である
必要はなく、徐々に変化させてせよい。要は第２
真性層の成膜温度の最高値より少なくとも第１真
性層の成膜温度の最高値を20〜250℃、好ましく
は50〜200℃低くすることである。 The deposition rate and film-forming temperature of the first intrinsic layer do not need to be constant and may be changed gradually. The point is the second
The maximum value of the film-forming temperature of at least the first intrinsic layer is lowered by 20 to 250°C, preferably 50 to 200°C, than the maximum value of the film-forming temperature of the intrinsic layer.
なお、第１真性層の堆積時における透明導電膜
へのプラズマの影響をさけるには、成膜温度の最
高値が10〜100℃で堆積するのが好ましく、10〜
180℃で堆積するのが好ましい。 In addition, in order to avoid the influence of plasma on the transparent conductive film during deposition of the first intrinsic layer, it is preferable to deposit the film at a maximum value of 10 to 100°C, and 10 to 100°C.
Preferably it is deposited at 180°C.
また、前記、第２真性層（高い成膜温度、６
Å／秒以上の堆積速度で成膜する層）を成膜する
条件は、たとえば圧力を0.2〜2.5Torrの範囲でグ
ロー放電を安定に維持可能な最大またはその近傍
にするのが好ましく、RFパワーSiH4ガス流量、
H2ガス流量は堆積速度６Å／秒以上、好ましく
は10Å／秒以上にすることが可能なように大きく
することが好ましい。ただしRFパワーのみは、
堆積速度、膜特性を得ることができる最小限が好
ましい。また成膜温度は200〜280℃程度で膜質が
良くなるが、なるべく低い温度で成膜するのが好
ましい。 In addition, the second intrinsic layer (high film forming temperature, 6
The conditions for forming a layer (which is deposited at a deposition rate of Å/sec or more) are, for example, preferably at or near the maximum pressure that can stably maintain glow discharge in the range of 0.2 to 2.5 Torr, and the RF power SiH4 gas flow rate,
Preferably, the H 2 gas flow rate is large enough to allow a deposition rate of 6 Å/sec or higher, preferably 10 Å/sec or higher. However, only the RF power
The minimum deposition rate and film properties that can be obtained are preferred. Although the film quality is improved at a film forming temperature of about 200 to 280°C, it is preferable to form the film at a temperature as low as possible.
本発明の方法を実施するための装置としては、
通常の容量結合型RF平行平板型CVD装置、誘導
結合型RFCVD装置、DC平行平板型CVD装置な
どがあげられるが、これらに限定されるものでは
ない。とくに平行平板型CVD装置において顯著
な効果がみられる。 The apparatus for carrying out the method of the present invention includes:
Usual capacitively coupled RF parallel plate type CVD devices, inductively coupled RF CVD devices, DC parallel plate type CVD devices, etc. may be mentioned, but the present invention is not limited to these. Particularly remarkable effects are seen in parallel plate type CVD equipment.
「実施例」
つぎに本発明の方法を実施例及び比較例に基づ
き説明するが、本発明はこれらにより何ら制限さ
れるものではない。"Examples" Next, the method of the present invention will be explained based on Examples and Comparative Examples, but the present invention is not limited by these in any way.
実施例１及び比較例１
ガラス板上に、スプレー法にて厚さ4000Åの
SnO2電極を形成、これを基板として用いた。Example 1 and Comparative Example 1 A film with a thickness of 4000 Å was applied onto a glass plate using a spray method.
A SnO 2 electrode was formed and used as a substrate.
該基板上に、基板温度30℃、CVD圧力
1.5Torr、SiH4／CH4の流量比が２／３、SiH4＋
CH4の合計流量に対してB2H6の正味流量が１％
になるようにして、RFパワー密度10mW／cm2で
Ｐ型ａ−SiC：Ｈ層を100Å堆積させた後、成膜
温度100℃（一定）、CVD圧力1TorrでSiH4ガス
を用いてRFパワー密度10mW／cm2で堆積速度1.6
Å／秒にてｉ型ａ−Si：Ｈ層（第１真性層）を
200Å堆積させた。 On the substrate, substrate temperature 30℃, CVD pressure
1.5 Torr, SiH 4 /CH 4 flow rate ratio is 2/3, SiH 4 +
The net flow rate of B 2 H 6 is 1% of the total flow rate of CH 4
After depositing a P-type a-SiC:H layer of 100 Å at an RF power density of 10 mW/ cm2 , the RF power was increased using SiH4 gas at a deposition temperature of 100°C (constant) and a CVD pressure of 1 Torr. Deposition rate 1.6 at density 10mW/ cm2
i-type a-Si:H layer (first intrinsic layer) at Å/sec
200 Å was deposited.
ついで、成膜温度235℃（一定）、CVD圧力
1.0ToorでSiH4ガスを用いてRFパワー密度
70mW／cm2で堆積速度13.8Å／秒にてｉ型ａ−
Si：Ｈ層（第２真性層）を60000Å堆積させた。
さらに成膜温度235℃（一定）、CVD圧力2Torr
にて、SiH4流量１に対してPH3を0.01、H2を30
になるように導入し、RFパワー密度70mW／cm2
でｎ型μc−Si：Ｈ層を300Å堆積させ、電極とし
てA1を真空蒸着法により1000Å堆積させて、１
cm2の面積を有する太陽電池を作製した。なおこの
ときの半導体層堆積に要した時間の合計は20分で
あつた。ちなみにｉ型ａ−Si：Ｈ層の高速成膜を
行わず２〜３Å／秒の堆積速度で成膜した場合の
時間の合計は80分であつた。 Then, the film formation temperature was 235℃ (constant), and the CVD pressure was
RF power density using SiH4 gas at 1.0Toor
I-type a- at 70mW/ cm2 and deposition rate 13.8Å/sec
A Si:H layer (second intrinsic layer) was deposited to a thickness of 60000 Å.
Furthermore, the film formation temperature is 235℃ (constant), and the CVD pressure is 2Torr.
At , PH 3 is 0.01 and H 2 is 30 for SiH 4 flow rate 1.
The RF power density is 70mW/ cm2 .
An n-type μc-Si:H layer was deposited to a thickness of 300 Å, and A1 was deposited to a thickness of 1000 Å as an electrode by vacuum evaporation.
A solar cell with an area of cm 2 was fabricated. Note that the total time required for depositing the semiconductor layer at this time was 20 minutes. Incidentally, when the i-type a-Si:H layer was not formed at high speed but was formed at a deposition rate of 2 to 3 Å/sec, the total time was 80 minutes.
得られた太陽電池の特性をAM−１、
100mW／cm2のソーラーシミユレーターを用いて
測定すると、Fsc16.0mA、Voc0.88V、F.F.58％、
η8.17％であつた。 The characteristics of the obtained solar cell were AM-1,
When measured using a 100mW/ cm2 solar simulator, Fsc16.0mA, Voc0.88V, FF58%,
η was 8.17%.
また比較用試料として、第１真性槽を堆積しな
い以外は実施例１と同様な条件にて太陽電池を作
製した。その特性を測定したところJsc14mA、
Voc0.7V、F.F.38％、η3.7％であつた。なおこの
ときの半導体槽堆積時間は18分程度であつた。 Further, as a comparative sample, a solar cell was produced under the same conditions as in Example 1 except that the first intrinsic tank was not deposited. When its characteristics were measured, it was Jsc14mA.
Voc was 0.7V, FF was 38%, and η was 3.7%. Note that the semiconductor tank deposition time at this time was about 18 minutes.
「発明の効果」
本発明の方法により半導体装置を製造すると、
製造時間を大巾に短縮でき、かつVoc，Jsc，F.
F.，ηがそれぞれ著しく改善された半導体装置を
得ることができる。"Effects of the Invention" When a semiconductor device is manufactured by the method of the present invention,
Manufacturing time can be drastically reduced, and Voc, Jsc, F.
A semiconductor device with significantly improved F. and η can be obtained.
Claims (1)
半導体を第１不純物ドープ層、真性層、第１不純
物ドープ層と反対の導電タイプの第２不純物ドー
プ層を順次堆積するプロセスに於いて、真性層を
堆積する際に、初めに堆積する厚さ80Å〜1000Å
の部分を第１真性層、残りの真性層の部分を第２
真性層とし、第２真性層の堆積速度が６Å／秒以
上、第１真性層の堆積速度が４Å／秒以下で、且
つ第１真性層の成膜温度の最高値が10℃〜100℃
であり且つ第２真性層の成膜温度の最高値より20
〜250℃低くすることを特徴とする半導体装置の
製造方法。 ２ 第１不純物ドープ層の成膜温度の最高値が10
〜100℃で、且つ前記第１真性層の成膜温度の最
高値と同じか或いはそれ以下である特許請求の範
囲第１項記載の製造方法。 ３ 第１と第２の少なくとも一方の不純物ドープ
層ａ−SiC：Ｈ（アモルフアスシリコンカーバイ
ド）またはμc−Si：Ｈ（微結晶化アモルフアスシ
リコン）である特許請求の範囲第１項又は第２項
記載の製造方法。[Claims] 1. A first impurity-doped layer, an intrinsic layer, and a second impurity-doped layer of a conductivity type opposite to the first impurity-doped layer are sequentially deposited on a transparent conductive film. In the process, when depositing the intrinsic layer, the initial deposit thickness is 80 Å to 1000 Å.
The part of the intrinsic layer is the first intrinsic layer, and the remaining part of the intrinsic layer is the second intrinsic layer.
An intrinsic layer, the deposition rate of the second intrinsic layer is 6 Å/sec or more, the deposition rate of the first intrinsic layer is 4 Å/sec or less, and the maximum film forming temperature of the first intrinsic layer is 10 ° C to 100 ° C.
and 20 from the highest value of the film forming temperature of the second intrinsic layer.
A method for manufacturing a semiconductor device characterized by lowering the temperature by ~250°C. 2 The maximum value of the film formation temperature of the first impurity doped layer is 10
2. The manufacturing method according to claim 1, wherein the temperature is 100 DEG C. and the same as or lower than the highest value of the film forming temperature of the first intrinsic layer. 3. Claim 1 or 2, wherein at least one of the first and second impurity doped layers is a-SiC:H (amorphous silicon carbide) or μc-Si:H (microcrystallized amorphous silicon). Manufacturing method described in section.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60242288A JPS62101083A (en) | 1985-10-28 | 1985-10-28 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60242288A JPS62101083A (en) | 1985-10-28 | 1985-10-28 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62101083A JPS62101083A (en) | 1987-05-11 |
| JPH0562830B2 true JPH0562830B2 (en) | 1993-09-09 |
Family
ID=17087019
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60242288A Granted JPS62101083A (en) | 1985-10-28 | 1985-10-28 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62101083A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR910007465B1 (en) * | 1988-10-27 | 1991-09-26 | 삼성전관 주식회사 | Making method of solar cell of amorphous silicon |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56167370A (en) * | 1980-05-26 | 1981-12-23 | Mitsubishi Electric Corp | Amorphous solar cell |
| JPS57159070A (en) * | 1981-03-26 | 1982-10-01 | Sumitomo Electric Ind Ltd | Manufacture of photo electromotive force element |
| JPS59107574A (en) * | 1982-12-13 | 1984-06-21 | Agency Of Ind Science & Technol | Manufacture of amorphous silicon solar cell |
-
1985
- 1985-10-28 JP JP60242288A patent/JPS62101083A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56167370A (en) * | 1980-05-26 | 1981-12-23 | Mitsubishi Electric Corp | Amorphous solar cell |
| JPS57159070A (en) * | 1981-03-26 | 1982-10-01 | Sumitomo Electric Ind Ltd | Manufacture of photo electromotive force element |
| JPS59107574A (en) * | 1982-12-13 | 1984-06-21 | Agency Of Ind Science & Technol | Manufacture of amorphous silicon solar cell |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62101083A (en) | 1987-05-11 |
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