JPS5559753A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5559753A
JPS5559753A JP13162978A JP13162978A JPS5559753A JP S5559753 A JPS5559753 A JP S5559753A JP 13162978 A JP13162978 A JP 13162978A JP 13162978 A JP13162978 A JP 13162978A JP S5559753 A JPS5559753 A JP S5559753A
Authority
JP
Japan
Prior art keywords
type
axis
layer
main surface
resistance layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13162978A
Other languages
Japanese (ja)
Other versions
JPS639380B2 (en
Inventor
Yoshiharu Nakajima
Fumihito Inoue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP13162978A priority Critical patent/JPS5559753A/en
Publication of JPS5559753A publication Critical patent/JPS5559753A/en
Publication of JPS639380B2 publication Critical patent/JPS639380B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/0802—Resistors only

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Bipolar Transistors (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To lessen resistance regulation, by arranging semiconductor resistors along an axis inclining at an angle of approximate 45 deg. from a [110] axis in one main surface of a semiconductor monocrystal substrate of a Si monolithic-IC, etc. or an axis crossing at right agles with the axis. CONSTITUTION:An N-type Si layer 2 is grown on a main surface of a monocrystal P-type Si substrate 1, which uses a [110] crystal plane as a main surface, in an epitaxial shape, and an N-type resistance layer 5 is formed by making up a P-type isolation region 4. A P-type resistance layer 3 is built up by diffusing P-type impurities into the N-type epitaxial layer. The Si substrate has orientation flat in the b1 direction shown in the figure or in the b2 direction rectangular to b1 direction. The N-type resistance layer 5 is formed in the direction that the longitudinal direction is parallel or rectangular to the b1 or b2 direction, and the P-type resistance layer 3 is made up in the direction that tilts at an angle of 45 deg. in these direction. Thus, the variation of resistance value due to stress in case of assembly and molding can be eliminated.
JP13162978A 1978-10-27 1978-10-27 Semiconductor device Granted JPS5559753A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13162978A JPS5559753A (en) 1978-10-27 1978-10-27 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13162978A JPS5559753A (en) 1978-10-27 1978-10-27 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS5559753A true JPS5559753A (en) 1980-05-06
JPS639380B2 JPS639380B2 (en) 1988-02-29

Family

ID=15062508

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13162978A Granted JPS5559753A (en) 1978-10-27 1978-10-27 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5559753A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02144960A (en) * 1988-11-28 1990-06-04 Matsushita Electron Corp Semiconductor resistance device
US4971926A (en) * 1984-08-28 1990-11-20 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5028794A (en) * 1973-07-13 1975-03-24

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5028794A (en) * 1973-07-13 1975-03-24

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4971926A (en) * 1984-08-28 1990-11-20 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device
JPH02144960A (en) * 1988-11-28 1990-06-04 Matsushita Electron Corp Semiconductor resistance device

Also Published As

Publication number Publication date
JPS639380B2 (en) 1988-02-29

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