JPS5637654A - Semiconductor element container - Google Patents
Semiconductor element containerInfo
- Publication number
- JPS5637654A JPS5637654A JP11332879A JP11332879A JPS5637654A JP S5637654 A JPS5637654 A JP S5637654A JP 11332879 A JP11332879 A JP 11332879A JP 11332879 A JP11332879 A JP 11332879A JP S5637654 A JPS5637654 A JP S5637654A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- container
- semiconductor element
- cap
- ceramic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
- H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Abstract
PURPOSE:To improve the accuracy of the external shape of a semiconductor element container of the type containing a semiconductor element in a recess formed on the surface of a laminated ceramic and sealing it with a cap by extending the periphery of container externally from the cap while maintaining the surface of placing the element as the same level as the periphery of the container. CONSTITUTION:The first ceramic layer 1 is formed of laminate ceramics, and a second ceramic layer 3 of ring shape is formed thereon as projected. Thus, a semiconductor element container is formed. Then, a semiconductor element 6 is soldered to the central portion on the surface 7 of the first layer 1 as surrounded by the second layer 3, and an electrode is connected to a metallized layer 2 formed on the first layer 2 using a fine bonding wire 8. Thereafter, an external lead wire 5 is connected to the end of the metallized layer 2 passing through the wall of the layer 3, and a cap 9 is fixed onto the surface of the second layer 3 using a low melting poing glass seal layer 10. Since the container may deform due to the sintering treatment in this configuration when forming the container, an externally extended exposed portion 4 is formed on the first layer 1 upon production of the container, and the deformation can be thus reduced at the container.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11332879A JPS5637654A (en) | 1979-09-04 | 1979-09-04 | Semiconductor element container |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11332879A JPS5637654A (en) | 1979-09-04 | 1979-09-04 | Semiconductor element container |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5637654A true JPS5637654A (en) | 1981-04-11 |
Family
ID=14609448
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11332879A Pending JPS5637654A (en) | 1979-09-04 | 1979-09-04 | Semiconductor element container |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5637654A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015216322A (en) * | 2014-05-13 | 2015-12-03 | 日本電気硝子株式会社 | Manufacturing method of ceramic-glass composite package, and ceramic-glass composite package |
-
1979
- 1979-09-04 JP JP11332879A patent/JPS5637654A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015216322A (en) * | 2014-05-13 | 2015-12-03 | 日本電気硝子株式会社 | Manufacturing method of ceramic-glass composite package, and ceramic-glass composite package |
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