JPS5627933A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5627933A
JPS5627933A JP10335879A JP10335879A JPS5627933A JP S5627933 A JPS5627933 A JP S5627933A JP 10335879 A JP10335879 A JP 10335879A JP 10335879 A JP10335879 A JP 10335879A JP S5627933 A JPS5627933 A JP S5627933A
Authority
JP
Japan
Prior art keywords
opening part
etching
region
condition
opening
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10335879A
Other languages
Japanese (ja)
Inventor
Shuji Kondo
Kazuhiko Tsuji
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP10335879A priority Critical patent/JPS5627933A/en
Publication of JPS5627933A publication Critical patent/JPS5627933A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching

Abstract

PURPOSE:To enable to control precisely the opening condition of an opening part of a semiconductor device when a minute opening part is to be formed in an insulating film provided on the semiconductor substrate by a method wherein an opening part for monitoring to afford the standard of judgement with regard to the etching condition is provided to judge visually the etching condition. CONSTITUTION:When a chip region 5 and a scribe grid part 15 are provided in a semiconductor substrate, and for example, an opening part is to be provided in a region 10 on the chip region 5 by etching an SiO2, masks 31 are formed on the parts excepting the region 10 and a monitor region 16 on the scribe grid part 15 to perform an etching process. The finishing time of etching is confirmed by detecting the changing state of surface condition of the opening part 16 from hydrophilic to hydrophobic. By forming the monitor opening part 16 by the process mentioned above having enough magnitude being able to confirm visually, although the opening part to be provided in the chip region 5 is too minute to be visual, the etching condition can be grasped precisely, so that the etching condition of the opening part can easily be controlled.
JP10335879A 1979-08-14 1979-08-14 Manufacture of semiconductor device Pending JPS5627933A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10335879A JPS5627933A (en) 1979-08-14 1979-08-14 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10335879A JPS5627933A (en) 1979-08-14 1979-08-14 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5627933A true JPS5627933A (en) 1981-03-18

Family

ID=14351900

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10335879A Pending JPS5627933A (en) 1979-08-14 1979-08-14 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5627933A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0712152A1 (en) * 1994-11-10 1996-05-15 Fuji Electric Co. Ltd. Semiconductor device and method for its manufacture

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4837225A (en) * 1971-09-14 1973-06-01
JPS5225574A (en) * 1975-08-21 1977-02-25 Mitsubishi Electric Corp Production method of semiconsuctor device
JPS5320770A (en) * 1976-08-10 1978-02-25 Nec Corp Production of thin film fine patterns

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4837225A (en) * 1971-09-14 1973-06-01
JPS5225574A (en) * 1975-08-21 1977-02-25 Mitsubishi Electric Corp Production method of semiconsuctor device
JPS5320770A (en) * 1976-08-10 1978-02-25 Nec Corp Production of thin film fine patterns

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0712152A1 (en) * 1994-11-10 1996-05-15 Fuji Electric Co. Ltd. Semiconductor device and method for its manufacture
US5869372A (en) * 1994-11-10 1999-02-09 Fuji Electric Co., Ltd. Method of manufacturing a power semiconductor device

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