JPS56146247A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS56146247A
JPS56146247A JP3807080A JP3807080A JPS56146247A JP S56146247 A JPS56146247 A JP S56146247A JP 3807080 A JP3807080 A JP 3807080A JP 3807080 A JP3807080 A JP 3807080A JP S56146247 A JPS56146247 A JP S56146247A
Authority
JP
Japan
Prior art keywords
layer
groove
type silicon
substrate
injected
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3807080A
Other languages
English (en)
Other versions
JPS6227744B2 (ja
Inventor
Takeshi Fukuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP3807080A priority Critical patent/JPS56146247A/ja
Priority to EP81301189A priority patent/EP0036764B1/en
Priority to DE8181301189T priority patent/DE3175640D1/de
Priority to IE631/81A priority patent/IE52351B1/en
Publication of JPS56146247A publication Critical patent/JPS56146247A/ja
Priority to US06/455,327 priority patent/US4497665A/en
Publication of JPS6227744B2 publication Critical patent/JPS6227744B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/763—Polycrystalline semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76888—By rendering at least a portion of the conductor non conductive, e.g. oxidation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Element Separation (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Recrystallisation Techniques (AREA)
JP3807080A 1980-03-25 1980-03-25 Manufacture of semiconductor device Granted JPS56146247A (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP3807080A JPS56146247A (en) 1980-03-25 1980-03-25 Manufacture of semiconductor device
EP81301189A EP0036764B1 (en) 1980-03-25 1981-03-19 A semiconductor device with a v-groove insulating isolation structure and a method of manufacturing such a device
DE8181301189T DE3175640D1 (en) 1980-03-25 1981-03-19 A semiconductor device with a v-groove insulating isolation structure and a method of manufacturing such a device
IE631/81A IE52351B1 (en) 1980-03-25 1981-03-20 A semiconductor device with a v-groove insulating isolation structure and a method of manufacturing such a device
US06/455,327 US4497665A (en) 1980-03-25 1983-01-03 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3807080A JPS56146247A (en) 1980-03-25 1980-03-25 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS56146247A true JPS56146247A (en) 1981-11-13
JPS6227744B2 JPS6227744B2 (ja) 1987-06-16

Family

ID=12515223

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3807080A Granted JPS56146247A (en) 1980-03-25 1980-03-25 Manufacture of semiconductor device

Country Status (5)

Country Link
US (1) US4497665A (ja)
EP (1) EP0036764B1 (ja)
JP (1) JPS56146247A (ja)
DE (1) DE3175640D1 (ja)
IE (1) IE52351B1 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59155944A (ja) * 1983-02-25 1984-09-05 Mitsubishi Electric Corp 半導体装置の製造方法

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58105551A (ja) * 1981-11-20 1983-06-23 Fujitsu Ltd 半導体装置
US4610730A (en) * 1984-12-20 1986-09-09 Trw Inc. Fabrication process for bipolar devices
US4849371A (en) * 1986-12-22 1989-07-18 Motorola Inc. Monocrystalline semiconductor buried layers for electrical contacts to semiconductor devices
JPS6467945A (en) * 1987-09-08 1989-03-14 Mitsubishi Electric Corp Wiring layer formed on buried dielectric and manufacture thereof
CN1034228C (zh) * 1993-08-04 1997-03-12 株洲冶炼厂 一种自萃除有色金属的富铁有机相中除铁的方法
DE19538005A1 (de) * 1995-10-12 1997-04-17 Fraunhofer Ges Forschung Verfahren zum Erzeugen einer Grabenisolation in einem Substrat
US20110241185A1 (en) * 2010-04-05 2011-10-06 International Business Machines Corporation Signal shielding through-substrate vias for 3d integration

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3956033A (en) * 1974-01-03 1976-05-11 Motorola, Inc. Method of fabricating an integrated semiconductor transistor structure with epitaxial contact to the buried sub-collector
US4037306A (en) * 1975-10-02 1977-07-26 Motorola, Inc. Integrated circuit and method
US4048649A (en) * 1976-02-06 1977-09-13 Transitron Electronic Corporation Superintegrated v-groove isolated bipolar and vmos transistors
DE2837800A1 (de) * 1978-08-30 1980-03-13 Philips Patentverwaltung Verfahren zum herstellen von halbleiterbauelementen
JPS5534442A (en) * 1978-08-31 1980-03-11 Fujitsu Ltd Preparation of semiconductor device
US4214918A (en) * 1978-10-12 1980-07-29 Stanford University Method of forming polycrystalline semiconductor interconnections, resistors and contacts by applying radiation beam
US4269636A (en) * 1978-12-29 1981-05-26 Harris Corporation Method of fabricating self-aligned bipolar transistor process and device utilizing etching and self-aligned masking
JPS6043024B2 (ja) * 1978-12-30 1985-09-26 富士通株式会社 半導体装置の製造方法
EP0030286B1 (de) * 1979-11-23 1987-09-09 Alcatel N.V. Dielektrisch isoliertes Halbleiterbauelement und Verfahren zur Herstellung
US4295924A (en) * 1979-12-17 1981-10-20 International Business Machines Corporation Method for providing self-aligned conductor in a V-groove device
US4260436A (en) * 1980-02-19 1981-04-07 Harris Corporation Fabrication of moat resistor ram cell utilizing polycrystalline deposition and etching

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59155944A (ja) * 1983-02-25 1984-09-05 Mitsubishi Electric Corp 半導体装置の製造方法

Also Published As

Publication number Publication date
IE810631L (en) 1981-09-25
IE52351B1 (en) 1987-09-30
JPS6227744B2 (ja) 1987-06-16
EP0036764A3 (en) 1984-01-18
EP0036764B1 (en) 1986-11-20
US4497665A (en) 1985-02-05
EP0036764A2 (en) 1981-09-30
DE3175640D1 (en) 1987-01-08

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