JPS56112741A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS56112741A
JPS56112741A JP1565080A JP1565080A JPS56112741A JP S56112741 A JPS56112741 A JP S56112741A JP 1565080 A JP1565080 A JP 1565080A JP 1565080 A JP1565080 A JP 1565080A JP S56112741 A JPS56112741 A JP S56112741A
Authority
JP
Japan
Prior art keywords
film
groove
infinitesimal
occurrence
leakage current
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1565080A
Other languages
Japanese (ja)
Inventor
Akira Kurosawa
Kenji Taniguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CHIYOU LSI GIJUTSU KENKYU KUMIAI
CHO LSI GIJUTSU KENKYU KUMIAI
Original Assignee
CHIYOU LSI GIJUTSU KENKYU KUMIAI
CHO LSI GIJUTSU KENKYU KUMIAI
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CHIYOU LSI GIJUTSU KENKYU KUMIAI, CHO LSI GIJUTSU KENKYU KUMIAI filed Critical CHIYOU LSI GIJUTSU KENKYU KUMIAI
Priority to JP1565080A priority Critical patent/JPS56112741A/en
Publication of JPS56112741A publication Critical patent/JPS56112741A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76227—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials the dielectric materials being obtained by full chemical transformation of non-dielectric materials, such as polycristalline silicon, metals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To form a high performance element isolating region for preventing the occurrence of an infinitesimal leakage current by forming an alumina film preferably contacted to the peripheral wall of a groove. CONSTITUTION:A thermal oxide film 2 is grown on a P<-> type silicon substrate 1, with a resist pattern 3 formed thereon as a mask, the film 2 and the substrate 1 are etched, and the groove 5 is opened thereat. An aluminum film is then accurated on the entire surface by a vacuum evaporation process, and an aluminum film 61 on the resist pattern 3 and an aluminum film 62 in the groove 6 are formed. Thereafter, anodic oxidation is conducted in aqueous oxalic acid solution to convert only the film 62 in the groove 5 into an alumina film 7. Consequently, the pattern 3 is dissolved and removed, the film 61 thereon is lifted off, the film 2 is further removed, and the element isolating region 8 is formed. Thus, it can prevent the occurrence of the infinitesimal leakage current.
JP1565080A 1980-02-12 1980-02-12 Manufacture of semiconductor device Pending JPS56112741A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1565080A JPS56112741A (en) 1980-02-12 1980-02-12 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1565080A JPS56112741A (en) 1980-02-12 1980-02-12 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS56112741A true JPS56112741A (en) 1981-09-05

Family

ID=11894588

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1565080A Pending JPS56112741A (en) 1980-02-12 1980-02-12 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS56112741A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010059737A (en) * 1999-12-30 2001-07-06 박종섭 Method for forming isolation layer of semiconductor device
CN103681446A (en) * 2012-09-10 2014-03-26 中国科学院微电子研究所 Shallow groove isolation structure and manufacturing method thereof
EP2775528A1 (en) * 2013-03-05 2014-09-10 Imec Passivated III-V or Ge fin-shaped field effect transistor
US11075123B2 (en) * 2019-09-16 2021-07-27 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming isolation structure having improved gap-fill capability

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010059737A (en) * 1999-12-30 2001-07-06 박종섭 Method for forming isolation layer of semiconductor device
CN103681446A (en) * 2012-09-10 2014-03-26 中国科学院微电子研究所 Shallow groove isolation structure and manufacturing method thereof
EP2775528A1 (en) * 2013-03-05 2014-09-10 Imec Passivated III-V or Ge fin-shaped field effect transistor
US9425314B2 (en) 2013-03-05 2016-08-23 Imec Passivated III-V or Ge fin-shaped field effect transistor
US11075123B2 (en) * 2019-09-16 2021-07-27 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming isolation structure having improved gap-fill capability

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