JPS56100517A - Flip-flop circuit - Google Patents

Flip-flop circuit

Info

Publication number
JPS56100517A
JPS56100517A JP335880A JP335880A JPS56100517A JP S56100517 A JPS56100517 A JP S56100517A JP 335880 A JP335880 A JP 335880A JP 335880 A JP335880 A JP 335880A JP S56100517 A JPS56100517 A JP S56100517A
Authority
JP
Japan
Prior art keywords
input
circuit
inverted
precedence
outputs
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP335880A
Other languages
Japanese (ja)
Inventor
Akira Kaneko
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP335880A priority Critical patent/JPS56100517A/en
Publication of JPS56100517A publication Critical patent/JPS56100517A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits

Abstract

PURPOSE:To obtain an asynchronous multiinut FF circuit where priorities are given to inputs in the control order, by connecting the output of one NOR circuit to the input of the other NOR circuit respectively and by using two OR circuits. CONSTITUTION:Input 10 has the precedence of input 12, and input 13 has the precedence of input 11; and for example, when nonpriority input R2 becomes 1 at time t1, outputs Q2 and Q2' are inverted. Then, when prioity input S1 becomes 1 at time t1, outputs Q2 and Q2' are inverted. Then, when nonpriority input R2 becomes 1 again at time t4, outputs Q2 and Q2' are not inverted. They are not inverted because of addition of an OR circuit to the next stage of the NOR circuit and the connecting method of this OR circuit. That is, input S1 keeps the precedence of input R2.
JP335880A 1980-01-16 1980-01-16 Flip-flop circuit Pending JPS56100517A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP335880A JPS56100517A (en) 1980-01-16 1980-01-16 Flip-flop circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP335880A JPS56100517A (en) 1980-01-16 1980-01-16 Flip-flop circuit

Publications (1)

Publication Number Publication Date
JPS56100517A true JPS56100517A (en) 1981-08-12

Family

ID=11555121

Family Applications (1)

Application Number Title Priority Date Filing Date
JP335880A Pending JPS56100517A (en) 1980-01-16 1980-01-16 Flip-flop circuit

Country Status (1)

Country Link
JP (1) JPS56100517A (en)

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