JPS56107630A - Delay time adjusting circuit - Google Patents

Delay time adjusting circuit

Info

Publication number
JPS56107630A
JPS56107630A JP1028380A JP1028380A JPS56107630A JP S56107630 A JPS56107630 A JP S56107630A JP 1028380 A JP1028380 A JP 1028380A JP 1028380 A JP1028380 A JP 1028380A JP S56107630 A JPS56107630 A JP S56107630A
Authority
JP
Japan
Prior art keywords
circuit
delay
gate
delay time
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1028380A
Other languages
Japanese (ja)
Inventor
Hidetsune Kurokawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP1028380A priority Critical patent/JPS56107630A/en
Publication of JPS56107630A publication Critical patent/JPS56107630A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/131—Digitally controlled

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)
  • Electronic Switches (AREA)

Abstract

PURPOSE:To obtain a delay time adjusting circuit which is inexpensive and can be changed to a monolithic IC, removing a defect of the delay circuit using a delay line, by constituting the delay circuit of cascade connection of the element to be used for the logical circuit. CONSTITUTION:A signal which has been input to the input terminal 60 of the delay circuit 10 is delayed by the gate circuits 101-103 by 3 stage portion of gate, and after that, it is output as a delay signal to the output terminal 70 through the selecting circuit 20. In this case, when the combination of the logical level ''0'' or ''1'' provided to the control terminals 80, 90 is changed suitably, a signal which is output to the output terminal 70 can be adjusted in terms of time at the delay time interval of 1 stage portion of gate at least. In this regard, in the delay circuit, the gate circuit 105 is used for equalizing the propagation delay time in each gate circuit by making the load same as that of the gate circuits 101-104 connected to the selecting circuit 20, and it can be omitted in case when the fluctuating load of the propagation delay time can be disregarded.
JP1028380A 1980-01-31 1980-01-31 Delay time adjusting circuit Pending JPS56107630A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1028380A JPS56107630A (en) 1980-01-31 1980-01-31 Delay time adjusting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1028380A JPS56107630A (en) 1980-01-31 1980-01-31 Delay time adjusting circuit

Publications (1)

Publication Number Publication Date
JPS56107630A true JPS56107630A (en) 1981-08-26

Family

ID=11745979

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1028380A Pending JPS56107630A (en) 1980-01-31 1980-01-31 Delay time adjusting circuit

Country Status (1)

Country Link
JP (1) JPS56107630A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0127172A2 (en) * 1983-05-31 1984-12-05 Siemens Aktiengesellschaft Phase shifting circuit for a clock signal
EP0181047A2 (en) * 1984-11-09 1986-05-14 Lsi Logic Corporation Delay control circuit and method for controlling delays in a semiconductor element
EP0183875A2 (en) * 1983-12-29 1986-06-11 Advantest Corporation Clocked logic device
JPS61242409A (en) * 1985-04-19 1986-10-28 Nec Corp Delay circuit
JPS62151237U (en) * 1986-03-17 1987-09-25
JPH01117514A (en) * 1987-10-30 1989-05-10 Fujitsu Ltd Semiconductor delay integrated circuit
JPH01158823A (en) * 1987-10-05 1989-06-21 General Electric Co <Ge> Digital-analog converter with switching function compensation
JPH01165212A (en) * 1987-10-05 1989-06-29 General Electric Co <Ge> Impedance converting circuit for multibit parallel digital signal circuit
WO2001078234A1 (en) * 2000-04-07 2001-10-18 Advantest Corporation Delay circuit and ring oscillator

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0127172A2 (en) * 1983-05-31 1984-12-05 Siemens Aktiengesellschaft Phase shifting circuit for a clock signal
EP0183875A2 (en) * 1983-12-29 1986-06-11 Advantest Corporation Clocked logic device
EP0181047A2 (en) * 1984-11-09 1986-05-14 Lsi Logic Corporation Delay control circuit and method for controlling delays in a semiconductor element
JPH0457247B2 (en) * 1985-04-19 1992-09-11 Nippon Electric Co
JPS61242409A (en) * 1985-04-19 1986-10-28 Nec Corp Delay circuit
JPH0441630Y2 (en) * 1986-03-17 1992-09-30
JPS62151237U (en) * 1986-03-17 1987-09-25
JPH01158823A (en) * 1987-10-05 1989-06-21 General Electric Co <Ge> Digital-analog converter with switching function compensation
JPH01165212A (en) * 1987-10-05 1989-06-29 General Electric Co <Ge> Impedance converting circuit for multibit parallel digital signal circuit
JPH01117514A (en) * 1987-10-30 1989-05-10 Fujitsu Ltd Semiconductor delay integrated circuit
WO2001078234A1 (en) * 2000-04-07 2001-10-18 Advantest Corporation Delay circuit and ring oscillator
US6717479B2 (en) 2000-04-07 2004-04-06 Advantest Corporation Delay circuit and ring oscillator
DE10164839B4 (en) * 2000-04-07 2005-05-25 Advantest Corp. Delay circuit for ring oscillator in which delay routes are connected parallel with input terminal
DE10196066B4 (en) * 2000-04-07 2009-09-03 Advantest Corp. delay circuit
JP4729228B2 (en) * 2000-04-07 2011-07-20 株式会社アドバンテスト Delay circuit and ring oscillator

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