JPS56123189A - Separating circuit for interpolated multiple signal - Google Patents
Separating circuit for interpolated multiple signalInfo
- Publication number
- JPS56123189A JPS56123189A JP2713180A JP2713180A JPS56123189A JP S56123189 A JPS56123189 A JP S56123189A JP 2713180 A JP2713180 A JP 2713180A JP 2713180 A JP2713180 A JP 2713180A JP S56123189 A JPS56123189 A JP S56123189A
- Authority
- JP
- Japan
- Prior art keywords
- coil
- output
- coupled
- delay line
- adjusting circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000007787 solid Substances 0.000 abstract 2
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N9/00—Details of colour television systems
- H04N9/77—Circuits for processing the brightness signal and the chrominance signal relative to each other, e.g. adjusting the phase of the brightness signal relative to the colour signal, correcting differential gain or differential phase
- H04N9/78—Circuits for processing the brightness signal and the chrominance signal relative to each other, e.g. adjusting the phase of the brightness signal relative to the colour signal, correcting differential gain or differential phase for separating the brightness signal or the chrominance signal from the colour television signal, e.g. using comb filter
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Processing Of Color Television Signals (AREA)
Abstract
PURPOSE:To eliminate cross color by applying a signal across a voltage-dividing load to the intermediate load point of the anti-resonate coil of an output transducer when separating a luminance signal and color signal by using an ultrasonic solid delay line. CONSTITUTION:The output of voltage-dividing load 4 connected to antiresonate coil 5 coupled with input transducer 3 of ultrasonic solid delay line 2 is supplied to level adjusting circuit 8. On the other hand, antiresonate coil 9 is coupled with output transducer 3' and loads 10 and 10' are connected to both the terminals of this coil 9. Then the output of level adjusting circuit 8 is coupled with the middle point between loads 10 and 10'. Thus, the variation in bias current of the emitter follower is prevented owing to the variation in the volume value of level adjusting circuit 8 due to a loss of delay line 2, so that the generation of cross color can be eliminated.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2713180A JPS56123189A (en) | 1980-03-04 | 1980-03-04 | Separating circuit for interpolated multiple signal |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2713180A JPS56123189A (en) | 1980-03-04 | 1980-03-04 | Separating circuit for interpolated multiple signal |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS56123189A true JPS56123189A (en) | 1981-09-28 |
JPH0255996B2 JPH0255996B2 (en) | 1990-11-28 |
Family
ID=12212494
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2713180A Granted JPS56123189A (en) | 1980-03-04 | 1980-03-04 | Separating circuit for interpolated multiple signal |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56123189A (en) |
-
1980
- 1980-03-04 JP JP2713180A patent/JPS56123189A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPH0255996B2 (en) | 1990-11-28 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS57121345A (en) | Pulse noise eliminating circuit | |
EP0233786A3 (en) | Circuit for providing a controlled resistance | |
JPS6454809A (en) | Asynchronous flip-flop | |
JPS56107630A (en) | Delay time adjusting circuit | |
JPS56166612A (en) | Level shifting circuit | |
JPS56123189A (en) | Separating circuit for interpolated multiple signal | |
JPS6486220A (en) | Feeding-back circuit | |
JPS5754430A (en) | Integrated circuit | |
JPS56166613A (en) | Voltage to current converting circuit | |
JPS5643833A (en) | Switching circuit for complementary characteristic | |
JPS573431A (en) | Complementary mos logical circuit | |
JPS5523553A (en) | Input/output control circuit | |
JPS6468006A (en) | Power amplifier provided with fader vr | |
JPS5525275A (en) | Facsimile system | |
JPS57197930A (en) | Logical circuit | |
JPS533767A (en) | Input-output-insulation circuit using photocoupler | |
JPS54100211A (en) | Active 2-4 line converter circuit | |
JPS5730412A (en) | Voltage comparison circuit | |
JPS5568729A (en) | Input circuit with input level decision | |
JPS57196871A (en) | Full-wave rectifying circuit | |
JPS54159246A (en) | Resistance value output circuit | |
EP0375665A3 (en) | A pulse delay circuit | |
JPS5799810A (en) | Signal controller | |
JPS56162539A (en) | Signal-line driving circuit | |
JPS5539918A (en) | Voltage and current output circuit |