JPS5523553A - Input/output control circuit - Google Patents

Input/output control circuit

Info

Publication number
JPS5523553A
JPS5523553A JP9573378A JP9573378A JPS5523553A JP S5523553 A JPS5523553 A JP S5523553A JP 9573378 A JP9573378 A JP 9573378A JP 9573378 A JP9573378 A JP 9573378A JP S5523553 A JPS5523553 A JP S5523553A
Authority
JP
Japan
Prior art keywords
output
input
control circuit
circuit
mode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9573378A
Other languages
Japanese (ja)
Inventor
Hisatsugu Ito
Kosaku Uota
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP9573378A priority Critical patent/JPS5523553A/en
Publication of JPS5523553A publication Critical patent/JPS5523553A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To reduce the number of I/O terminals by connecting a terminal, which is used for input and output commonly, to the connection point between a switch and a control object in the I/O control circuit of a micro processor.
CONSTITUTION: The I/O mode of control circuit 100 is switched by signal S1; and in the output mode, output buffer circuit 101 outputs signal S2 to control light emission diode 33 through load reistance 29. In the input mode, the output of output buffer circuit 101 is inhibited, and the circuit becomes a high-impedance state, and terminal P0 is determined by the switching state of weitch 21, thus determining output signal S3 of input buffer 102.
COPYRIGHT: (C)1980,JPO&Japio
JP9573378A 1978-08-05 1978-08-05 Input/output control circuit Pending JPS5523553A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9573378A JPS5523553A (en) 1978-08-05 1978-08-05 Input/output control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9573378A JPS5523553A (en) 1978-08-05 1978-08-05 Input/output control circuit

Publications (1)

Publication Number Publication Date
JPS5523553A true JPS5523553A (en) 1980-02-20

Family

ID=14145666

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9573378A Pending JPS5523553A (en) 1978-08-05 1978-08-05 Input/output control circuit

Country Status (1)

Country Link
JP (1) JPS5523553A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58142461A (en) * 1982-02-18 1983-08-24 Nec Corp Data system selection circuit
JPS58186862A (en) * 1982-04-23 1983-10-31 Nec Corp Data system selecting circuit
JPS58186863A (en) * 1982-04-23 1983-10-31 Nec Corp Data system selecting circuit
JPS58167903U (en) * 1982-04-29 1983-11-09

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58142461A (en) * 1982-02-18 1983-08-24 Nec Corp Data system selection circuit
JPS58186862A (en) * 1982-04-23 1983-10-31 Nec Corp Data system selecting circuit
JPS58186863A (en) * 1982-04-23 1983-10-31 Nec Corp Data system selecting circuit
JPS58167903U (en) * 1982-04-29 1983-11-09

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