JPS56149820A - Analog automatic equalizer and its driving method - Google Patents
Analog automatic equalizer and its driving methodInfo
- Publication number
- JPS56149820A JPS56149820A JP5390180A JP5390180A JPS56149820A JP S56149820 A JPS56149820 A JP S56149820A JP 5390180 A JP5390180 A JP 5390180A JP 5390180 A JP5390180 A JP 5390180A JP S56149820 A JPS56149820 A JP S56149820A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- analog
- automatic equalizer
- fetched
- multiplied
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B3/00—Line transmission systems
- H04B3/02—Details
- H04B3/04—Control of transmission; Equalising
- H04B3/14—Control of transmission; Equalising characterised by the equalising network used
- H04B3/142—Control of transmission; Equalising characterised by the equalising network used using echo-equalisers, e.g. transversal
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Filters That Use Time-Delay Elements (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
Abstract
PURPOSE:To make a system smal and to realize its low cost, high reliability and also wide band, by constituting an automatic equalizer of an analog circuit. CONSTITUTION:A signal which has been inputted to the terminal 2 is inputted to the analog delay line 1. On the analog delay line 1 are provided taps, and a signal which has been fetched from each tap is multiplied by a weighting coefficient in the analog multipliers 5-1, 5-2.... The weighting coefficient can be obtained by mutliplying in the multiplier 6-M a signal which has multiplied an error signal E (n) generated from a difference between an output signal Y (n) and a reference signal a (n), by an analog constant (u), by a signal which has been fetched from the taps 4-1, 4-2..., and always updating a signal which has been obtained in this way, by the arithmetic circuit consisting of substracters 20-1, 20-2... and CCD memory elements 21-1, 21-2....
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5390180A JPS56149820A (en) | 1980-04-23 | 1980-04-23 | Analog automatic equalizer and its driving method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5390180A JPS56149820A (en) | 1980-04-23 | 1980-04-23 | Analog automatic equalizer and its driving method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS56149820A true JPS56149820A (en) | 1981-11-19 |
JPS6329444B2 JPS6329444B2 (en) | 1988-06-14 |
Family
ID=12955615
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5390180A Granted JPS56149820A (en) | 1980-04-23 | 1980-04-23 | Analog automatic equalizer and its driving method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56149820A (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5215212A (en) * | 1975-07-23 | 1977-02-04 | Codex Corp | Receiver |
JPS53111258A (en) * | 1977-01-10 | 1978-09-28 | Texas Instruments Inc | Programmable frequency conversion filter |
-
1980
- 1980-04-23 JP JP5390180A patent/JPS56149820A/en active Granted
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5215212A (en) * | 1975-07-23 | 1977-02-04 | Codex Corp | Receiver |
JPS53111258A (en) * | 1977-01-10 | 1978-09-28 | Texas Instruments Inc | Programmable frequency conversion filter |
Also Published As
Publication number | Publication date |
---|---|
JPS6329444B2 (en) | 1988-06-14 |
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