JPS6329444B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an automatic equalizer that processes signals entirely using analog values.

Conventionally used automatic equalizers are digital automatic equalizers, which have major problems such as large system size, large power consumption, high price, low reliability, and narrow band.

The configuration and operation of a conventional digital automatic equalizer will be explained below with reference to FIG. 401 is an input terminal of a digital automatic equalizer to which an input signal is applied. Although the input signal is originally a digital signal, the signal waveform is distorted due to intersymbol interference in the transmission path. 402 is an N-bit analog-to-digital converter (hereinafter referred to as A/D converter) which converts the distorted input signal into an N-bit digital signal. Reference numeral 403 denotes an N-bit storage circuit composed of RAM or the like, and storage element 403-k (k=1, 2,
...M, M is a natural number) The N-bit digital signal is held and stored sequentially. 405-k or 406-
k, (k=1, 2,...M) are the N-bit digital signals X(n-k), (k=1, 2,...M) output from the storage element 403-k, and the N-bit digital signals X(n-k), (k=1, 2,...M), respectively. Digital weighting coefficient Wk, (k=1, 2,...M)
Alternatively, multiplying X(n-k) by, for example, an N-bit digital signal u·E(n),
For example, it is a 2N-1 bit digital multiplier.
Here, u is a constant, E(n) is a digital difference signal to be described later, and n is a sample number indicating the calculation period.

407-k, (k=1, 2...M) is the weighting coefficient
Wk(n) is stored, and a new N-bit weighting factor Wk(n+
1) from the Wk(n) and the output signal u.E(n).X(n-k) of the multiplier 406-k. That is, the Wk(n+1) is Wk(n+1)=Wk(n)-u・E(n)・X(n-
k) is given by (1). The above equation is the basic calculation equation of an automatic equalizer called the so-called least squares method. 408 is the digital output Wk of the digital multiplier 405-k
This is a digital adder that adds (n)・X(n-k) from k-1 to M, and its output, that is, the digital output signal Y(n) of this digital automatic equalizer, is Y(n) = _M 〓 ^k=1 Wk(n)・X(n-k) (2) Given. 409 obtains the difference between the output signal Y(n) and an arbitrary digital signal a(n), and calculates the digital error signal E(n), that is, E(n)=Y(n)−a(n) ( 3) is a digital subtractor that obtains. 410 is the E(n)
This is a digital multiplier that multiplies u by the constant u to obtain u·E(n). The configuration of the conventional digital automatic equalizer has been described above. The components of the equalizer are 402, 403, 405-k, 406-k,
407-k, 408, 409, and 410 are all large-scale digital integrated circuits, so
It consumes a lot of power and is expensive. Therefore, it is completely impossible to further integrate a large number of these integrated circuits onto a semiconductor chip from the viewpoint of chip area, power consumption, yield, reliability, etc. As a result, until now, each component has 402, 40
3,...410 had to be arranged on a large number of printed boards and wired, resulting in a large system, unsuitable for mass production, and high prices, among other drawbacks. Furthermore, since signal processing in each component is performed bit by bit, there is a fundamental drawback of digital processing, namely extremely slow calculation speed. was completely impossible.

SUMMARY OF THE INVENTION An object of the present invention is to provide an analog automatic equalizer and a method for driving the same that can solve many of the problems of the conventional digital automatic equalizers at once.

According to the present invention, there is provided an analog delay line including a plurality of delay stages for delaying a signal, a tap for non-destructively detecting a delayed signal provided incidentally to the delay stage, and each tap of the analog delay line. and another input terminal to which each weighting coefficient corresponding to each tap is derived. a first analog multiplier provided in the first analog multiplier; an analog weighting coefficient circuit provided for each tap for supplying each of the weighting coefficients to the first analog multiplier; and each of the first analog multipliers. an analog adder comprising a plurality of input terminals each connected to an output terminal and for adding each output signal of the first analog multiplier; and a positive input terminal connected to the output terminal of the analog adder. and a negative input terminal to which any analog signal is led,
a first analog subtracter for calculating the difference between the analog adder output signal and an arbitrary signal; and an input terminal connected to the output terminal of the first analog subtracter, and an arbitrary analog constant derived therefrom. a second analog multiplier for multiplying the first subtracter output signal by an arbitrary signal; and an input to which the second analog multiplier output terminal is connected. and another input terminal to which each analog delay signal of the analog delay line is guided, and provided for each tap to perform multiplication of the second multiplier output signal and each analog delay signal. and a third multiplier, and each of the analog weighting coefficient circuits provided for each of the taps outputs at least two signals, each of which includes a charge injection means and a charge detection means capable of holding an output signal for a certain period of time. one comprising a charge transfer element having a charge accumulation region and a second analog subtracter, the negative side input terminal of the second analog subtracter being connected to the corresponding output terminal of the third analog multiplier; , directing the second analog subtracter output to charge injection means of the charge transfer element;
It is further characterized in that the signal obtained by the charge detection means of the charge transfer element is supplied to the first analog multiplier and is also guided to the positive input terminal of the second analog subtracter. An analog automatic equalizer is obtained.

Further, according to the present invention, in the analog automatic equalizer, a non-destructive detection tap of each delay stage in the delay line outputs a delayed signal at regular intervals, and each delayed signal is outputted by the first multiplier. and the corresponding weighting coefficient supplied from the charge transfer element, the output signal of the first multiplier is added by the adder, and the output signal of the adder is added to the output signal of the automatic equalizer. signal, calculate the difference between the output signal and any signal using the first subtracter, further multiply the output of the first subtracter by a constant using the second multiplier, Next, the third multiplier multiplies each of the delayed signals by the second multiplier output to produce a weighting factor correction signal at the output of the third multiplier; 2
A subtracter calculates the difference between the weighting coefficient held in the charge detecting means of the charge transfer element and the weighting coefficient correction signal, and inputs the output of the subtracter to the charge transfer element to perform the next step. A method for driving an automatic equalizer is obtained, which is characterized in that the period is outputted as a weighting coefficient.

The analog equalizer according to the present invention does not require an A/D converter, and each component, such as a multiplier, an adder, a subtracter, and a delay line, is an analog equalizer that is completely unrelated to the number of bits as described above. Since it is an element, it is possible to achieve miniaturization, faster signal processing, and lower power consumption. Therefore, an automatic equalizer can be easily integrated on one chip, and it is also possible to realize an automatic equalizer that is mass-producible, low-cost, and highly reliable. Furthermore, unlike a digital equalizer, there is no need to perform a calculation for each bit, so the calculation time can be extremely shortened. Therefore, since it can be driven at high speed, it becomes possible to expand the range of applications of the automatic equalizer to the field of high-band data communication, which was previously impossible. Hereinafter, the present invention will be explained using the drawings.

FIG. 2 shows a specific configuration of the analog automatic equalizer of the present invention. 1 is an analog delay line, and 2 is an input terminal of the delay line. 3-k(k
=1, 2, . . . M) can delay a digital signal, that is, an analog signal, distorted by intersymbol interference by a certain period of time at each delay stage of the delay line.
Means for non-destructively detecting a delayed signal is provided for each delay stage. 4-k (k=1, 2,...M)
indicates the tap position of the detection means. The analog output signal of the tap is denoted by X(n-k) similarly to the digital signal. Here n is a sampling number. 5-k (k=1, 2,...M) and 6
-k (k=1, 2,...M) are the tap output signals X(n-k), (k=1, 2,...M) and analog value weighting coefficients Wk(n), (k=1 , 2,...M)
Or the tap output signal X(n-k) and uE(n)
It is an analog multiplier that multiplies the . Here, u is an analog constant and E(n) is an analog error signal. 7-k (k=1, 2,...M) stores the weighting coefficient Wk(n) and stores a new analog weighting coefficient Wk(n+) to be used next after a certain period of time.
1), (k=1, 2,...M) and then holds the new analog weighting coefficient Wk (n+1), and an analog subtracter 20-k
(k=1, 2,...M) and analog memory element 2
1-k (k=1, 2,...M). 8 is the analog output signal Wk of the analog multiplier 5-k
An analog adder that adds (n)・X(n-k),
The output signal Y(n) of the analog adder 8 is given by equation (2) and is obtained from the terminal 11. 9 obtains the difference between the output signal Y(n) and an arbitrary analog signal a(n), and obtains the analog error signal E(n) given by equation (3).
This is an analog subtracter that obtains . Reference numeral 10 denotes an analog multiplier that multiplies the analog error signal E(n) by the analog constant u to obtain uE(n).

Next, the operation of the analog weighting coefficient circuit 7-k will be described. The analog weighting coefficient for calculating equation (1)
Wk(n) is applied to one input terminal of the analog multiplier 5-k and the analog subtracter 20-k while being held in the analog storage element 21-k. At the same time, the output signal of the analog multiplier 6-k,
That is, the analog weighting coefficient correction signal u・E(n)・X
(n-k) is also applied to the other input terminal of the analog subtracter 20-k, the new analog weighting coefficient Wk (n+1) is given by equation (1), and the analog storage element 21-k It is held in 1 and used for calculations in the next period. The specific structure and driving method of the analog weighting coefficient circuit 7-k will be explained in detail below.

In addition, in the above explanation, analog automatic equalizer,
Analog multiplier, analog signal, etc. and “analog”
However, in the following explanation, the word "analog" will be omitted for simplicity.

FIG. 3 shows an embodiment of the weighting coefficient circuit 7-k in FIG. 2. As already mentioned, the weighting coefficient circuit is composed of a subtracter 20-k and a memory element 21-k, and in this embodiment, the memory element 21 shown in FIG.
As a specific example of -k, a charge-coupled device (hereinafter referred to as CCD
) is used. The CCD storage element 21-
In k, 101 is a semiconductor substrate, 102 is an input diffusion layer provided as a charge injection source and has a conductivity type opposite to that of the substrate 101, 103, 104, 105,
106 are electrodes arranged on the substrate 101 via an insulating film 107, 108 is a floating diffusion layer having a conductivity type opposite to that of the substrate 101 provided for collecting signal charges, and 109 and 110 are floating diffusions. Together with the layer 108, a reset gate and drain are formed to form a reset MOSFET and periodically preset the floating diffusion layer 108 to a constant potential. 111 is a MOSFET for detecting potential changes in the floating diffusion layer 108, and 112 is a MOSFET.
For loads that constitute a source follower with 111
It is a MOSFET. In addition, in each of the above electrodes,
The electrode 103 is called an input gate electrode.
Corresponds to the input terminal of this CCD storage element 21-k,
The output of subtractor 20-k is derived. Further, the electrode 106 is usually called an output gate electrode, and is suitably biased with DC by a power source 113 so as to form a channel under which electric charges can pass. The other two electrodes 104 and 105 are well-known transfer electrodes, and transfer pulses, which will be described later, are applied from terminals 114 and 115, respectively. Furthermore, in FIG. 3, reference numeral 116 indicates a power source for DC biasing the reset drain, and reference numerals 117 and 118 indicate pulse voltage application terminals connected to input diffusion layer 102 and electrode 109, respectively.

Next, an outline of the operation of this CCD storage element 21-k will be described.

In the following description, for convenience, the conductivity type of the semiconductor substrate is assumed to be P type. FIG. 4 shows a CCD memory element 21-
An example of the drive pulse voltage waveform and output voltage waveform of k is shown. In the figure, 201 is the input diffusion layer 102
The pulse voltage applied to 202 and 203
204 indicates a transfer pulse applied to the transfer electrodes 104 and 105, 204 indicates a reset pulse applied to the gate 109 of the reset MOSFET, and 205 indicates a transfer pulse applied to the detection MOSFET 111 and the load MOSFET.
The output voltage waveform obtained at the output terminal 119 of the source follower composed of MOSFET 112 is shown.
Incidentally, as is well known, the transfer pulses 202 and 20
3, the low-level voltage 206 is usually set to a value close to the threshold voltage, and the high-level voltage 207 is set to a value sufficient to accumulate signal charges near the semiconductor surface under the electrode. Generally, the former voltage value is around 0 volts, and the latter voltage value is around 10 to 15 volts.

The CCD 21-k shown in FIG. 3 uses a potential balance method as a charge injection means. The potential balancing method forms a metering potential well under the second electrode;
There are several well-known methods of applying the input signal voltage as a voltage difference between the first electrode and the second electrode, but in the CCD of this embodiment,
The signal is applied to the input gate electrode 103 and the first transfer electrode 104 is used to form the metering potential well. In this case, a pulse voltage 201 is applied to the input diffusion layer 102 such that the transfer pulse 202 applied to the transfer layer pole 104 becomes a low potential within a period 210 in which the voltage 207 is on the high level side. The voltage 208 on the low level side of this pulse 201
Normally, the high-level voltage 209 and the low-level voltage 206 of the transfer pulse are somewhat higher than the high-level voltage 207 of the transfer pulse. When a high level voltage of 207 is applied to the transfer electrode 104, when the input diffusion layer 102 becomes a low level voltage of 208,
Excess charge is transferred across the barrier under the input gate electrode 103 formed by the signal voltage to the transfer electrode 104.
It flows into a metering potential well formed below. Next, when the input diffusion layer 102 returns to the high level side voltage 209, the excess charge directly under the electrode 104 flows out to the input diffusion layer side until the surface potential directly under the electrode becomes equal to the surface potential under the electrode 103. The amount of charge injected into the high level well under the transfer electrode 104 in this way is transferred to the input gate electrode 103 during the period 210.
, that is, the output voltage of subtractor 20-k during period 210.
Now, let this voltage be Wk(n).

The charges injected into the potential well directly below the transfer electrode 104 as described above are first set to the high level side voltage 207 of the transfer pulse 203 at time _t1 , and then set the transfer pulse 202 to the low level side voltage 207 at time _t2. By setting the voltage to 206, the potential is transferred to the potential well below the adjacent transfer electrode 105 according to the well-known CCD principle, and the period 21 from time t ₂ to t ₃ is
2, it is accumulated under the electrode. Output gate electrode 10
An appropriate DC bias voltage 113 is applied to the transfer electrode 106, and a channel through which charges can pass is formed under the electrode, so the signal charge under the transfer electrode 106 is
When the transfer pulse 203 returns to the low level voltage 206 at time _t3 , it is transferred to the floating diffusion layer 108 that has been charged in advance by the reset MOST.
The floating diffusion layer 108 is activated by the power supply 116 connected to the reset drain 110 by setting the reset pulse 204 to a high level and making the channel under the reset gate 109 conductive in a period 211 before the signal charge is transferred. During the period 212, the reset pulse 204 is returned to the low level side and the lower part of the reset gate 109 is made non-conductive, so that it is preset to a constant potential determined by the voltage value of the drain power supply 116 and the amplitude of the reset pulse 204. Becomes a floating state.
Therefore, when signal charges are transferred from below the transfer electrode 105 at time _t3 , the potential of the floating diffusion layer 108 changes from the potential of the preset period 212 by a voltage proportional to the amount of signal charges (this (in the example it descends). This potential change in the floating diffusion layer 108 is detected by a source follower composed of MOSFETs 111 and 112, and is output as a change 220 in the output voltage 205 at a low impedance. Since the source follower has a high input impedance, the potential of the floating diffusion layer changed by the transfer of signal charges is then reset again by the reset pulse 204.
It is held until time t ₇ when becomes high level. Therefore, the change amount 220 is also maintained in the output voltage 205 from time t ₃ to time t ₇ . Needless to say, the change amount 220 is proportional to the amount of charge injected during the period 210, and as described above, this is the output of the subtractor 20-k during the period 210,
It is proportional to the voltage Wk(n). Therefore, the CCD storage element 21-k stores the output voltage of the subtracter 20-k sampled during the period 210 from time _t0 to _t1 .
Let Wk(n) be the periods 213 and 21 from time t ₃ to t ₇ .
It is retained and memorized for 4 days. From time t ₀ to t ₇
The operation of the CCD storage element 21-k has been explained, and among these, the times _{211, 212} , 212,
213 and 214 constitute one clock period of the CCD storage element. Note that the operation in the last period 214 of the clock cycle is exactly the same as the operation in period 210, and as described later, the weighting coefficient Wk (n+1) used in the calculation of the next period is sampled and transferred as a signal charge. Inject directly below the electrode 104.

Multipliers 5-k and 6-k are also shown in FIG. 3 to clarify the relationship between weighting coefficient circuit 7-k and other components shown in FIG. 2.

The output voltage 205 of the CCD storage element 21-k obtained at the output terminal 119 of the source follower consisting of MOSFETs 111 and 112 is led to the multiplier 5-k, while being input to the positive input terminal 120 of the subtracter 30-k. be done. Moreover, the output uE of the multiplier 6-k is connected to the negative input terminal 121 of the subtracter 30-k.
(n)·X(n−k) is input. Therefore, the output terminal 122 of the subtracter 20-k is supplied from the output voltage Wk(n) of the CCD storage element 21-k to the multiplier 6.
- the weighting coefficient correction signal uE derived from k
Output voltage Wk (n+
1) is obtained. The output voltage is further sent to the input gate electrode 103 of a CCD storage element 21-k, which is sampled during the last period 214 of the clock period (times _t6 to _t7 ).
Wk (n+1) is the time of the next cycle starting from time t ₇
Retains memory from _t9 .

As described above, the weighting coefficient input to the multiplier 5-k is modified by the weighting coefficient correction signal obtained at the output of the multiplier 6-k every one clock cycle of the CCD storage element 21-k, and It is stored and held in the CCD storage element 21-k in cycles and used for calculations.

Next, the overall operation of the automatic equalizer according to the present invention will be explained using an example of a driving method. For convenience of explanation, the delay line 1 in FIG. 2 is a CCD which is a typical example of a delay element that can easily constitute a delay line with taps.
Although this is done assuming that it is composed of , this is just an example. FIG. 5 shows an example of the configuration of a CCD with taps used in the following explanation. In the same figure, the area surrounded by the dashed line is one delay stage corresponding to 3-k in FIG.
Reference numerals 1 to 307 designate electrodes arranged on a semiconductor substrate (not shown) via an insulating film (not shown) in accordance with the well-known CCD concept. Electrodes 302, 3 forming one transfer stage 3-k
03, 304, the first electrode 302 is commonly connected to the first electrode of all other transfer stages (for example, electrode 305 corresponds to this) and is connected to the first phase of the first phase. Similarly, the second electrode 303 is commonly connected to the second phase clock line 309 along with the second electrodes of all other transfer stages (such as electrode 306). ing. The first phase and the second phase
Transfer pulses as described later are applied to the phase clock lines 308 and 309, respectively, and the signal charges in each delay stage are transferred all at once by the transfer pulses. On the other hand, diagonally shaded electrodes 301, 304, and 307 placed at the end of each delay stage are signal detection electrodes (referred to as detection electrodes) called "floating electrodes" and are set to a constant potential every clock cycle. At the same time, the electrode is brought into a floating state, and the signal charge transferred below the electrode is detected as a change in the potential of the electrode. For this reason, the detection electrode has
A detection circuit consisting of MOSFETs 310, 311, and 312 is provided. MOSFET310 is
This is a reset switch for periodically presetting the electrode to a constant potential before the signal charge is transferred to the detection electrode 304, and the source is the detection electrode 304.
4, and the gate and drain are connected to a driving line 31 whose gate and drain are commonly wired to all delay stages.
3 and 314. A reset pulse (described later) for controlling the conduction state of the reset switch 310 is applied to the drive line 313.
4 is supplied with a DC voltage. Also MOSFET3
11 and 312 constitute a source follower, and the source follower outputs the potential change of the detection electrode 304 with low impedance. The output terminal 315 of the source follower corresponds to tap position 4-k in FIG. 2 and is led to multipliers 5-k and 6-k. Note that 316 is a source follower power supply line that is commonly wired to all delay stages.

FIG. 6 is for explaining an example of the method of driving an automatic equalizer according to the present invention, in which a CCD as shown in FIG. 5 is used as the delay line 1, and the memory element 2 is
1-k as explained in Figures 3 and 4.
FIG. 4 is a timing diagram showing the driving of each part of the automatic equalizer and signal voltage waveforms when a CCD is used. In the same figure, 401 and 402 are the fifth
Transfer pulse voltages are applied to the two-phase clock lines 308 and 309 of the CCD shown in the figure, and 403 is the reset pulse voltage applied from the drive line 314 to the MOSFET reset switch 310 connected to the detection electrode 304 of the CCD. , 404 is the output voltage of the source follower composed of MOSFETs 311 and 312, which corresponds to the tap output signal obtained at the tap position 4-k in FIG. However, the above drive and signal waveforms are
This is an example in which the CCD shown in FIG. 5 is constructed on a P-type semiconductor substrate, and an N-channel element is used for the MOSFET reset switch 310. In the transfer pulse voltages 401 and 402, the voltage 406 on the low level side is set to a value close to the threshold voltage, and the voltage 407 on the high level side is set to a value sufficient to accumulate signal charges under the electrode. A voltage value of 10 to 15 volts is generally used as the latter voltage value near 0 volts. Further, the reset pulse 403 is set to a high level voltage 408 when the reset switch 310 is made conductive, and is set to a low level voltage 409 when the reset switch 310 is made non-conductive. Furthermore, in FIG. 6, 405 is a weighting coefficient voltage appearing at the output terminal 122 of the subtracter 20-k shown in FIG. 3, which is input to the CCD storage element.
Since the driving of the CCD storage element 21-k and the output signal voltage waveform have already been described in detail, the same reference numerals as in FIG. 4 will be given and the explanation will be omitted. In addition, in the diagram
In the times indicated by t ₀ , t ₁ , t ₂ . . . , the same reference numerals as in FIG. 3 indicate that the times are the same as the times in FIG. 3.

Hereinafter, the explanation will be made based on FIG. 6 and also using FIGS. 2 to 5.

Transfer pulses 401, 402 at times t ₁ and t ₂
When the voltage 407 reaches a high level one after another, the signal charge accumulated under the detection electrode 301 of the previous stage is transferred to the two transfer electrodes 302 and 303 of the delay stage 3-k.
Move down. At this time, there is no signal charge directly below the detection electrode 303, and by using this period, the reset pulse 403 is set to a high level from time _t2 to time _t3 , and the reset switch 310 is brought into a conductive state, thereby changing the detection electrode 303 to a DC voltage. is set to the potential of the drive line 314 to which is supplied. The value of the DC voltage supplied to the drive line 314 is generally 6 to 8 volts. In addition, in order to completely charge the battery at this time, it is necessary to set the voltage 408 on the high level side of the reset pulse to a value sufficiently larger than the voltage of the drive line 314 (6 to 8 volts). . At time _t3 , the reset pulse 403 returns the voltage 409 to the low level side and turns the reset switch 310 into a non-conductive state, so that the detection electrode 304 is preset and at the same time becomes a floating state. Further, at time _t4 , when the transfer pulse 402 becomes a low-level voltage 406, the signal charge is transferred below the detection electrode 304, so the potential of the detection electrode, which is already in a floating state, is preset. time t ₃
The potential between t4 and _t4 changes by a voltage proportional to the amount of signal charge transferred below the electrode (in this example, it decreases). Note that in order to prevent the reset switch 310 from becoming conductive during the signal detection period, the voltage 4 on the low level side of the reset pulse 403 is
09 needs to be a value sufficiently lower than the lowest potential appearing on the detection electrode 304 due to a potential change when the maximum amount of signal charge is transferred. time
The signal charge transferred below the detection electrode 304 at t ₄ is then transferred to the voltage 4 on the high level side of the transfer pulse 301.
Since the signal is accumulated and held under the detection electrode until time _t6 , which is 07, the detection electrode maintains a potential change proportional to the signal charge amount during this period.

The potential change of the detection electrode 304 described above is
Tap position 4- as an output voltage 404 via a source follower consisting of MOSFETs 311 and 312.
Since the output voltage 404 is taken out at time k, a change 410 proportional to the signal charge amount is also held from time t ₄ to time t ₇ . That is, in the output voltage 404 obtained at the tap position 4-k of each delay stage 3-k, the voltage value between time _t4 and time _t7 corresponds to the delayed signal X(n-k), The delayed signal X(n-k) is input to a multiplier 5-k.
On the other hand, the output voltage 205 of the storage element 21-k of the weighting coefficient circuit 7-k is also input to the multiplier 5-k, but the CCD storage element 21-k is input from time t ₃ to t ₇ as described above. Until then, Wk(n) is held and stored. Therefore, between times _t4 and _t7 , both the delayed signal X(n-k) and the weighting coefficient Wk(n) are input to the multiplier 5-k, and the multiplier 5
An output signal of Wk(n)·X(n−k) is obtained at the output of −k. However, the output voltage 404 of the delay stage 3-k and the output voltage 205 of the CCD storage element 21-k also include a DC voltage component unrelated to the delay signal X(n-k) and the weighting coefficient Wk(n) voltage component. I'm here. This DC voltage component is generated when the CCD transfers the signal charge superimposed on the bias charge, and when used for calculations, it is necessary to remove the DC voltage component using a level shifter, etc. be.

Output signal Wk (n) x (n-) of each multiplier 5-k
k) are added in the adder 8 and become the output signal Y(n) of the automatic equalizer. The output signal Y(n) is further sent to a subtracter 9. An arbitrary signal a(n) is subtracted from the output signal Y(n) to the subtracter 9, and an error signal E(n) is output. The error signal E(n) is led to a multiplier 10 and multiplied by a constant u to become an output signal uE(n) of the multiplier 10. The output signal uE(n) of the multiplier 10 is passed through the conductor 12 to each delay stage 3.
-k is input to a multiplier 6-k provided corresponding to the signal. On the other hand, the output voltage 404 is also input to the multiplier 6-k from the tap position 4-k of the delay stage 3-k. Since the delayed signal X(n-k) is held, the weighting coefficient correction signal uE(n)X(n-k) is obtained as the output of the multiplier 6-k.
The weighting coefficient correction signal is then sent to the negative input terminal 121 of the subtracter 20-k forming the weighting coefficient circuit 7-k.

The positive input terminal 120 of the subtracter 20-k has
The output voltage 205 of the CCD storage element 21-k is input, and the output voltage 205 is applied to the multiplier 5 described above.
The weighting coefficient Wk used in the calculation at −k
(n), the output terminal 122 of the subtracter 20-k has Wk(n)-uE shown in equation (1).
(n)・X(n-k) or the next period (n+1)
The modified weighting factor Wk used for the calculation in
(n+1) is obtained. It is assumed that the arithmetic procedure described above from when the signal charge is transferred to each delay stage 3-k of the delay line 1 until obtaining the modified weighting coefficient Wk(n+1) is completed at time _t5 . Furthermore, the time
The time required from t ₄ to t ₅ is determined by the operation (response) speed of the multiplier, adder, subtractor, etc. used in the operation. In this case, the output voltage 405 of the subtracter 20-k
will output Wk(n+1) at time _t5 . The time before this, that is, the value of the shaded period in the voltage 405 has no meaning as a weighting coefficient. This is because no signal charge is accumulated under the detection electrode of each delay stage 3-k during the period from time _t1 to time _t4 , and therefore the delayed signal X(n
-k) is not obtained at the tap position 4-k, and in the period from time _t4 to _t5 , the weighting coefficient correction signal uE(n)・X(n-k) is obtained. This is because the calculation has not been completed.
Between time t ₆ and time _{t 7} when sampling is performed by the CCD storage element 21-k, the calculation has already been completed.
Since Wk(n+1) has been obtained, the weighting coefficients can be updated without any problem.

By repeating the above procedure, the difference between the output signal Y(n) of the automatic equalizer and the arbitrary signal a(n),
That is, the error signal E(n) gradually decreases, and as a result, Y(n) and a(n) match, and at the point when the error signal E(n) becomes zero, the weighting coefficient Wk(n)
settles down to a constant value, and the equalization ends here.

[Brief explanation of the drawing]

FIG. 1 shows the configuration of a conventional digital automatic equalizer, where 401 is an input terminal of the equalizer;
402 is an analog-digital converter, 403 is an analog-to-digital converter;
405-k and 406-k are digital multipliers; 407-k is a digital subtracter; 408 is a digital adder;
09 is a digital subtracter, and 410 is a digital multiplier. FIG. 2 is a block diagram showing the specific configuration of the automatic equalizer according to the present invention, where 1 is a delay line, 2 is a delay line,
is the input terminal of the delay line, 3-k (k=1, 2,...
M) is each delay stage of the delay line 1, 4-k (k=1,
2,...M) are tap positions for non-destructively extracting the delayed signal of each delay stage, 5-k and 6-k (k=
1, 2,...M) is a multiplier, 7-k (k=1, 2,...M) is a multiplier,
...M) is a weighting coefficient circuit consisting of a subtracter 20-k and a storage element 21-k, 8 is an adder, 9 is a subtracter, 1
0 is a multiplier, 11 is an equalizer output terminal, and the pre-equalized signal input to terminal 2 is output to terminal 11 after being equalized. FIG. 3 is a block diagram showing an example of the memory circuit 7-k, and as a specific example of the memory element 21-k.
The case where a CCD is used is shown, 101 is a semiconductor substrate,
102 is an input diffusion layer, 103, 104, 105,
Reference numeral 106 designates electrodes arranged on the substrate 101 via an insulating film 107, 108 a floating diffusion layer, 109 a reset gate, 110 a reset drain, and 111 and 112 MOSFETs constituting a source follower. FIG. 4 shows the CCD storage element 21 shown in FIG.
201 is a pulse voltage applied to the input diffusion layer 102, and 202 and 203 are the electrode 1.
Transfer pulse voltage applied to 04 and 105,
204 is a reset pulse applied to the reset gate 109, 205 is MOSFET 111 and 112
This is the output voltage of the CCD storage element 21-k obtained at the output terminal 119 of the source follower composed of . FIG. 5 shows a configuration example of a CCD used as a specific example of delay line 1 in FIG. 2 in order to concretely explain the overall operation of the automatic equalizer according to the present invention, and 3-k is one delay stage. , 302, 303, 30
5, 306 is a transfer electrode, 301, 304, 307
is a detection electrode, 308 and 309 are clock lines,
310 is a MOSFET connected to the detection electrode 304
Reset switches, 313 and 314 are
MOSFET reset pulse application terminal and drain power supply of MOSFET reset switch 310, and 311 and 312 are MOSFETs forming a source follower. FIG. 6 is a timing diagram for explaining an example of the method for driving an automatic equalizer according to the present invention;
01 and 402 are transfer pulse voltages applied to the clock lines 308 and 309 of the CCD shown in FIG.
The reset pulse voltage applied to the MOSFET reset switch 310 from the drive line 313 is 4
04 is the tap output voltage of each delay stage 3-k obtained at the output terminal 315 of the source follower composed of MOSFETs 311 and 312, and 405 is the tap output voltage of the subtracter 3.
0-k output voltage.

Claims (1)

[Scope of Claims] 1. An analog delay line including a plurality of delay stages for delaying a signal, a tap for non-destructively detecting the delayed signal provided incidentally to the delay stages, and each of the analog delay lines. The tap has an input terminal connected to a tap and another input terminal to which each weighting coefficient corresponding to each tap is derived, and the tap is used to multiply the analog delay signal obtained at each tap by the corresponding weighting coefficient. a first analog multiplier provided for each tap; an analog weighting coefficient circuit provided for each tap for supplying each weighting coefficient to the first analog multiplier; a plurality of input terminals respectively connected to each output terminal;
an analog adder for adding up each output signal of the analog multiplier; a positive input terminal to which the output terminal of the analog adder is connected; and a negative input terminal to which an arbitrary analog signal is led; a first analog subtracter for calculating the difference between the analog adder output signal and an arbitrary signal; an input terminal to which the output terminal of the first analog subtracter is connected; and an arbitrary analog constant derived from the input terminal; a second analog multiplier for multiplying the first subtracter output signal by an arbitrary signal; and an input terminal to which the second analog multiplier output terminal is connected. and another input terminal to which each analog delay signal of the analog delay line is led, and a second multiplier provided for each tap for multiplying the second multiplier output signal by each analog delay signal. 3 multipliers;
The analog weighting coefficient circuit provided for each of the taps is a charge transfer element having at least two signal charge storage regions each including a charge injection means and a charge detection means capable of holding an output signal for a certain period of time. , a second analog subtracter, and connecting the negative input terminal of the second analog subtracter to the corresponding third analog multiplier output terminal; to the charge injection means of the charge transfer element, further supplying the signal obtained by the charge detection means of the charge transfer element to the first analog multiplier, and the positive input terminal of the second analog subtracter. An analog automatic equalizer characterized in that it is configured to lead to 2. An analog delay line equipped with a plurality of delay stages for delaying signals and a tap for detecting the delayed signal in a non-destructive manner attached to the delay stage, and an input connected to each tap of the analog delay line. a terminal and another input terminal to which each weighting coefficient corresponding to each tap is derived, and a terminal provided for each tap in order to multiply the analog delay signal obtained at each tap by the corresponding weighting coefficient. 1 analog multiplier, an analog weighting coefficient circuit provided for each tap for supplying each weighting coefficient to the first analog multiplier, and each connected to each output terminal of the first analog multiplier. a plurality of input terminals, the first
an analog adder for adding up each output signal of the analog multiplier; a positive input terminal to which the output terminal of the analog adder is connected; and a negative input terminal to which an arbitrary analog signal is led; a first analog subtracter for calculating the difference between the analog adder output signal and an arbitrary signal; an input terminal to which the output terminal of the first analog subtracter is connected; and an arbitrary analog constant derived from the input terminal; a second analog multiplier for multiplying the first subtracter output signal by an arbitrary signal; and an input terminal to which the second analog multiplier output terminal is connected. and another input terminal to which each analog delay signal of the analog delay line is led, and a second multiplier provided for each tap for multiplying the second multiplier output signal by each analog delay signal. 3 multipliers;
The analog weighting coefficient circuit provided for each of the taps is a charge transfer element having at least two signal charge storage regions each including a charge injection means and a charge detection means capable of holding an output signal for a certain period of time. , a second analog subtracter, and connecting the negative input terminal of the second analog subtracter to the corresponding third analog multiplier output terminal; to the charge injection means of the charge transfer element, further supplying the signal obtained by the charge detection means of the charge transfer element to the first analog multiplier, and the positive input terminal of the second analog subtracter. In the analog automatic equalizer configured to lead to the electric charge, the non-destructive detection tap of each delay stage in the delay line outputs a delayed signal at regular intervals, and the first multiplier combines each delayed signal and the electric charge. By multiplying by the corresponding weighting coefficient supplied from the transfer element,
The output signals of the multipliers are added by the adder, the output signal of the adder is used as the output signal of the automatic equalizer, and the difference between the output signal and an arbitrary signal is subtracted by the first subtraction. further, the second multiplier multiplies the output of the first subtracter by a constant, and then the third multiplier multiplies each delayed signal by the second multiplier. producing a weighting factor correction signal at the output of the third multiplier by multiplying the weight by the weight held in the charge detection means of the charge transfer element by the second subtractor; An automatic equalizer characterized in that the difference between the coefficient and the weighting coefficient correction signal is calculated, and the output of the subtracter is input to the charge transfer element to be output as a weighting coefficient in the next cycle. Driving method.