JPS5950560A - Charge transfer device - Google Patents

Abstract

PURPOSE:To contrive that the saturation of charges is difficult to generate at a transfer part even in the case of a plurality of input parts by a method wherein the value of input reference DC bias voltage is varied large and small by diode cut off method, according to the size of the maximum value of input signal. CONSTITUTION:The input signal Vin is impressed on an input diffused layer 12, a clock voltage phiG is impressed on an input gate electrode 18, and an input reference DC bias voltage VCC on the other input gate electrode 14. Then, signal charges proportional to the difference between the DC bias voltage VCC and the input signal Vin are injected and successively transferred. At that time, the value of the DC bias voltage VCC is varied large and small by a detection circuit 80 for the maximum voltage of the input signal, according to the size of the maximum value of the input signal Vin.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a charge transfer device that prevents charge that does not change over time from being injected as a signal charge and makes saturation of transfer charges less likely to occur, and that is particularly suitable for tapped CCDs. (hereinafter abbreviated as CCD).

As is well known, COD includes a semiconductor substrate and a group of electrodes insulated from the substrate, and the signal charges made of minority carriers accumulated in potential wells formed in the semiconductor substrate below these electrodes are transferred to the electrodes. This is a device that applies multiphase voltages to groups and sequentially transfers them in the longitudinal direction of the channel, and has many uses in the field of signal processing, such as as a delay line for analog signals.

There are various methods of inputting signal charges to the COD, but Fig. 1 shows the following:
The conventional input part structure of a CCD using the diode cutoff method is shown, in which 10 is a p-type silicon substrate, 11 is silicon oxide, 12 is an n-swelled diffusion layer, and 13 to 22 are gate electrodes. Gate electrodes 13-22 are generally made of aluminum, polycrystalline silicon, or the like. Silicon oxide 11 insulates substrate 10 and gate electrodes 13-22. Vin is the input signal voltage, VDD is the DC bias voltage, φG is the gate clock, VCC is the input reference (DC bias) voltage, φ
3. φ is a charge transfer clock. FIG. 2 shows the various clocks φ1 shown in FIG. φ7. The amplitude and phase of φG are shown. Figure 3 (a) * (b) , (C) , (
d) C is an explanatory diagram of the operation of the COD input section shown in FIG. 1. Figure (a) is a schematic diagram of the input section near the surface of the board.
, (e).

(d) is the time 1. shown in FIG. 2, respectively. , 1. ,
1. FIG. 3 is a diagram showing the potential and charge movement inside the substrate under the poles 16 to 22. n-type scattering layer 1
2, and at time t, the gate electrode 18 is activated by the gate clock φG as shown in FIG.
By opening the gate electrode, a charge proportional to the amplitude of the input signal is filled under the gate electrode 14 to which the input reference voltage VCC is applied. Next, at time t, the gate electrode 18 is closed by the gate clock φG, and the signal charge Qsig is accumulated in the potential well formed by the gate electrodes 1B, i4, and 19, as shown in FIG. This signal charge is transferred to the transfer clock φ4 at time t, as shown in FIG. 7 due to φ
By repeating the above operations, the signal charge Qsig corresponding to the magnitude of the input signal voltage Vin is sequentially input into the COD, and the signal charge Qsig is input to the inside of the COD under the expansion diffusion layer 12. potential 9'In, gate electrode 1
4 The internal potential below is ψ. When it is set to 0, the relationship between the internal potential ψln and the signal charge QsiH is as shown in FIG. When ψin>v(Hc), the internal potential ψ under the gate electrode 14 in FIG. 3(b) is smaller than the internal potential ψin under the n-swelled diffusion layer 12, so
At time t1, the area under the gate electrode 14 is not filled with charge. Therefore, in this case, Qsig=0. ψ.

≦ψin＜ψ. .

In this case, Qsig changes linearly with respect to ψIn. Also ψio〈ψ. In the case of , Q5□3 becomes larger than the maximum charge storage amount Qmax of the potential well in the transfer section of CCp, and therefore becomes saturated. Therefore, conventionally, in order to ensure a dynamic range, the DC voltage value of the input signal is set so that the internal potential under the n-swelled diffusion layer 12 is ψDC as shown in FIG.
He was walking with his legs crossed.

However, the conventional signal charge input method using the diode cut method has the following drawbacks.

Figure 5 is a block diagram of an input weighted transversal filter constructed using tapped CCD delay lines.
50 is an input terminal, 51 is an output terminal, 52 is a tapped delay line using a CCD, 56 to 56 are gain control circuits, τ
is the tap delay time interval. Here, the gain control circuit 53
If the conventional diode cutoff method explained in Figs. 1 to 4 is used as a method of inputting each of the output signals of ~56 to the tagged CCD delay line, the excess charge shown in Fig. 4 from each tap will also be reduced to α( Since the charge does not change over time and is not useful as a signal charge], the disadvantage is that the charge is likely to be saturated in the transfer section of the tapped CCD delay line.

Next, as a method of inputting signal charges to CC and D, a conventional example using a potential balance method, which aims to improve linearity and low noise characteristics, will be explained with reference to FIGS. 6 to 9. -60 in Figure 6
61 is a p-type silicon substrate, 61 is silicon oxide, 62 is an n-swelled diffusion layer, and 66 to 72 are gate electrodes. In this case too,
The gate electrode is formed of aluminum, polycrystalline silicon, or the like, and the silicon oxide 61 insulates the substrate and the gate electrode group. Vin is the input signal voltage, vDD, vsaC is the DC bias voltage, φ7. φ2 is a charge transfer clock SP is a sampling clock, and φ2 is a signal charge input clock. FIG. 7 shows various clocks φ7 shown in FIG. φ,,
The amplitude and phase of SP and φ- are shown. Figure 8(a), Φ)
1(C) and (d) are diagrams illustrating the operation of the charge input section according to the potential balance method shown in FIG. Figure (a) is the sixth
Schematic diagram of the vicinity of the board surface of the input section shown in the figure, Figure (b) ~
(d) is the time t'o""'t'! shown in FIG. 3 shows potential and charge movement inside the substrate under gate electrodes 63 to 72 in FIG. At time t, the n-swelling diffusion layer 62
The lower internal potential is at the position shown by the single point K in Figure 8(b).

The sampling clock sP at time t:! pressure is VSPL
When the voltage changes from to VSPH, the internal potential under the 0-type diffusion layer 62 reaches the position shown by the solid line in FIG. Charges corresponding to the magnitude of the input signal voltage Vin are stored. At time t', the gate electrode 6
When the voltage of the signal charge input clock φi applied to 9 is 0
to ■G, and as shown in Figure (C), the gate electrode 6
In the potential well formed at 5.69 and 7o, Va-Vi
A signal charge Qsig proportional to n is accumulated, and thereafter, this signal charge Qsig is sequentially transferred by the transfer clock φ and φ as shown in Figure C).The above operation is repeated. As a result, signal charges QsIg are sequentially input into the CCD according to the magnitude of the input signal voltage Vin.
FIG.

In the case of Vtn>Va, the gate electrode 6 is
Since the internal potential under the gate electrode 68 does not fall below the internal potential under the gate electrode 68, it becomes -Qsig-〇, and if o≦V in < Vc, Qsig becomes V
It changes linearly with in. Also, Vin<V.

In the case of QsigfJ'', it becomes larger than the maximum charge storage amount Qmax of the potential well in the transfer section of the CCD, so it is saturated.Therefore, even when using the potential balance method, in order to ensure the dynamic range, the DC voltage value of the input signal is , was set near VDC shown in Figure 9. However,
In this case as well, a charge QDC corresponding to the DC voltage value VDC is always input, and the charge saturates in the transfer section of the CCD, especially in the case of a tab/tub delay line, making it impossible to obtain the correct output voltage. Otherwise, the same drawbacks as in the diode cano-off method will occur.

SUMMARY OF THE INVENTION An object of the present invention is to provide a charge transfer device that does not have the drawbacks of the conventional CCD described above, and is designed to prevent charge saturation in the transfer section even when there are a plurality of input sections.

In order to achieve the above object, in the present invention, in order to prevent the injection of charges that do not change over time and are not useful as signal charges, in the case of the diode cut-off method, the The input reference DC bias voltage value and, in the case of the potential balance method, the signal charge input clock voltage peak value are varied in magnitude.

FIG. 10 shows the part where the input reference (DC bias) voltage VCC is applied to the gate electrode 14 of the embodiment applied to the inventive diode-cannot-off method, and 80 in the figure indicates the maximum voltage value of the input signal voltage Vin. This is a maximum voltage detection circuit that detects the voltage and outputs a DC voltage proportional to its magnitude. FIG. 11 shows how the input reference voltage VCC applied to the gate electrode 14 changes according to the present invention when the amplitude of the input signal voltage ■in changes. FIG. 12 is a diagram showing the effects of this embodiment. ψ. . and ψ'cc indicate the internal potential under the gate electrode 14 when the input reference voltages are VCC and V'cc', respectively.

In this embodiment, when the input signal voltage Vin is a signal as shown by the solid line in FIG. 12, the input reference voltage becomes VCC, and the signal charge Qs follows the relationship shown by the solid line in FIG.
ig is input. − power, input signal voltage ■ln is the 8th
When the 5VC amplitude is small as shown by the broken line in the figure, the input reference voltage becomes Vcc, and the signal charge Qsig is input according to the relationship shown by the dashed line in FIG. As a result, the minimum value of the signal charge Qsig is always () regardless of the amplitude of the input signal voltage Vin, and no excess charge is sent to the transfer section of the COD.Compare with the conventional example shown in Fig. 4. It can be seen that charge saturation in the COD transfer section is less likely to occur.

Next, Section 13.1 describes an example in which the present invention is applied to the potential balance method.
This will be explained with reference to Figure 4.15. FIG. 13 shows the part that applies the signal charge input clock to the gate electrode 69 in this embodiment, and in the figure, 80 detects the maximum voltage value of the input signal and outputs a voltage proportional to the size of the input signal. The maximum voltage detection circuit 81 is a switch circuit controlled by the clock φ shown in FIG. φ; is the direct gate electrode 6
This is the clock applied to 9. The switch circuit 81 is controlled by φ'G so that it is connected to the maximum voltage detection circuit 80 side when the clock φ'0 is at a high level, and to the ground side when the clock φ'0 is at a low level. When the amplitude of the input signal voltage Vln changes, the gate electrode 6
The waveform of the clock φ; actually applied to the clock 9 is shown in the 14th part A. That is, the clock φB is synchronized with the clock φi and has peak values (Vc and VG) proportional to the maximum value (vmax and V product X) of the input signal voltage Vin. 1st
FIG. 5 is a diagram showing the effect of this embodiment. In the input method according to the present invention, when the input signal voltage Vin has a large amplitude as shown by the solid line in the diagram, the peak value of the clock φa becomes VG, and the signal charge Qs
ig is input. - power, input signal voltage Vin is 15th
In the case of a signal with a small amplitude as shown by the broken line in the figure, the peak value of the clock φδ is G, and the signal charge Qsig is input according to the relationship shown by the dashed line in FIG. As a result, the minimum value of the signal charge Qsig is the input signal voltage Vi
Regardless of the amplitude of n, it is always Qmtn, and only the minimum necessary charge is injected into the transfer section of the CCD.

Therefore, compared to the conventional example using the potential balance method shown in FIG. 9, charge saturation in the CCD transfer section is less likely to occur.

An example in which the potential balance method of the present invention is applied to each tap input section of the transversal filter shown in FIG. 5 is as follows.
It is shown in FIG. 56 is the same as in the case of Fig. 5 (gain control circuit, 64, 68, 69 are the gate electrodes as in the case of Fig. 6, 80 and 81 are the maximum voltage detection circuit and switch circuit respectively as in the case of Fig. 13) , 90.91 is resistance,
92 to 97 are n-MOSFET, q8ftp-MOSF
ET, 99 high inverter, ■in is the input signal of the gain control circuit 53, V'*nm1n is the minimum voltage value of the input signal Vin - VCOn is the control voltage that controls the gain of the gain control circuit 56, and Vc is the DC bias voltage. be. FIG. 17 is a diagram showing the relationship between the output voltage Vin and the control voltage VCOn of the gain control circuit 56 (which of course serves as an input to the filter) consisting of a 9° resistor and a 92.95 n-MO8FET. be. In the figure, 1 indicates the waveform of the output voltage Vin when the control voltage VCOn is V, and 2 indicates the control voltage is ■.

The waveform of the output voltage Vin is shown when VG1 is waveform 1.
is the maximum voltage value of Resistor 91 and n-M 08F E
Maximum voltage detection port for input signal configured with T 94.95 F! ! 580 inputs the control voltage vcon to the gate of the n-MO8FET 94, inputs the minimum voltage value V:nm1n of the input signal V'In to the gate of the n-MO8FET 95, and makes the value of the resistor 91 equal to the value of the resistor 9o. 1st
The output voltage is generated according to the curve shown by the parameter V'+nm1n in FIG. Therefore, this output voltage is always the maximum value of the output signal of the gain control circuit 53, ! Nee faY 7).

n -MO8FE T 96.97 Topp-MO8FE
In the switch circuit 81 constituted by T98, when the clock φ' is at a high level, the n-MO8FET97 and the p-MO8FET9B become conductive, and the n-MO8FET9
6 becomes non-conductive, the voltage value of the clock φ- which is its output becomes the output voltage of the maximum voltage detection circuit 8o. On the other hand, when clock φ; is at low level, n-MO8F
ET96 conducts, n-MO8FET97 and p-MO8
Since FET9B becomes non-conductive, the voltage value of clock φ becomes 0. Therefore, the waveform of the clock φ is as shown in FIG.

The effects of the embodiment shown in FIG. 16 will be explained with reference to FIGS. 18 and 19. FIG. 18 is a diagram showing the signal charge Qs'tg'Y when the two voltage waveforms 1 and 2 shown in FIG. 17 are input to the CCD using the conventional charge input method.

In the conventional input method, the peak value of the black signal applied to the gate electrode 69 is set to Vc (constant) so that a correct signal charge Qsig can be obtained even for waveform 2. Therefore, a DC charge of q is added to the signal charge Qsig for A101. - When the strength tree invention Z is implemented, as shown in FIG. 19, the peak value of the clock applied to the gate electrode 69 for waveform 1 becomes VGl, and the input signal voltages Vin and Q
Since the relationship of sig is as shown by the dashed line, no direct current charge q is generated in the signal charge Qsig, and saturation in the CCD transfer section is less likely to occur (compared to the conventional case).

As explained above, according to the present invention, in both the diode cano-off method and the potential balance method, input of excess DC charge for signal use is suppressed, and it can be used in a charge transfer device having multiple input sections. Also, charge saturation in the transfer section is less likely to occur.

[Brief explanation of drawings]

Figure 1 shows a conventional CCD using the diode cutoff method.
Input section structure example Figure 5 Figure 2 is a waveform diagram showing the amplitude and phase of the various clocks shown in Figure 1, Figure 3 (a), (b)
, (C) and (d) are explanatory diagrams of the charge input process in the same example, FIG. 4 is a diagram showing the relationship between input signals and signal charges in the same example, and FIG. 5 is a block diagram of the input weighted transversal filter. Figure 6 shows the conventional C in the case of potential balance method.
Example of structure of CD input section Fig. 5 Fig. 7 is a waveform diagram showing the amplitude and phase of the various clocks shown in Fig. 6, Fig. 8 (a), (b)
), (C). (d) is an explanatory diagram of the charge input process in the same example, FIG. 9 is a diagram showing the relationship 2 between the input signal and signal charge in the same example, and FIG.
The figure is an explanatory diagram of the charge input section of the embodiment of the present invention in the case of the diode cut-off method, and Fig. 11 is an explanatory diagram of the input reference (@flow bias) for supplementary input of the signal of the same embodiment and the change in pressure. , FIG. 12 is an explanatory diagram of the effect of the same embodiment, FIG. 13 is an explanatory diagram of the charge input section of the embodiment of the present invention in the case of the potential balance method, and FIG. 14 is a waveform diagram of the signal charge input clock of the same embodiment. , Fig. 15 is an explanatory diagram of the effect of the same embodiment, Fig. 16 is an explanatory diagram of each tap input section of a transversal filter implementing the present invention of the potential balance method, and Fig. 17 is a gain control circuit of the input section of the same filter. FIG. 18 is a signal charge diagram when the conventional technique is used for the input of the same filter, and FIG. 19 is a signal charge diagram when the present invention is applied to the input section of the filter. 12.62...N swelling diffusion layers 13-22, 63-72...Gate electrode 80...
Input signal maximum voltage detection circuit 81...Switch circuit φ0...Gate clock φ-2φ;...Gate clock VCC according to the present invention.
...Input reference (@current bias) voltage φ7. φ2...Transfer clock Vin...Input signal voltage Qsig...Signal charge/Figure 2/172 χJ 3 Figure 4 Figure 5 Figure 6 Figure VDv Vt'x Vc'e ~ l'ts2'zl
' off Figure 111 tθ'nol'noibar'f 8 figure off figure/θ figure 11 figure V sai/2 figure-i 73 figure/4 y\J O/j figure O/6 Figure 3 Sai/7 figure 107? illustrator/de illustrator

Claims (2)

[Claims] (1) comprising one or more charge injection portions consisting of an input diffusion layer and two or more input gate electrodes, applying an input signal to the input diffusion layer, applying a clock voltage to one of the input gate electrodes; An input reference DC bias voltage is applied to the other one, and a signal charge proportional to the difference between this DC bias voltage and the input signal is injected. A charge transfer device that sequentially transfers charges, characterized in that the DC bias voltage value is changed in magnitude in response to the magnitude of a maximum value of an input signal. (2) One or more charge injection portions consisting of an input diffusion layer and two or more input gate electrodes are provided, and an input signal is applied to one of the input gate electrodes and a clock voltage is applied to the other one. In a charge transfer device that injects a signal charge proportional to the difference between the voltages applied to these two gate electrodes and sequentially transfers the signal charge, the peak value of the clock voltage is increased or decreased in accordance with the magnitude of the maximum value of the input signal. A charge transfer device characterized in that the charge transfer device changes to