CA1210097A - Signal transfer system using a charge transfer device - Google Patents
Signal transfer system using a charge transfer deviceInfo
- Publication number
- CA1210097A CA1210097A CA000436571A CA436571A CA1210097A CA 1210097 A CA1210097 A CA 1210097A CA 000436571 A CA000436571 A CA 000436571A CA 436571 A CA436571 A CA 436571A CA 1210097 A CA1210097 A CA 1210097A
- Authority
- CA
- Canada
- Prior art keywords
- region
- electrode
- charge transfer
- signal
- electrical signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
- G11C19/282—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements with charge storage in a depletion layer, i.e. charge coupled devices [CCD]
- G11C19/285—Peripheral circuits, e.g. for writing into the first stage; for reading-out of the last stage
Abstract
ABSTRACT OF THE DISCLOSURE
A charge transfer device has one or more charge injection areas each having an input diffusion layer and two or more input gate electrodes. An input signal is applied to the input diffusion layer, a clock voltage is applied to one of the input gates and an input reference voltage is applied to the other input gate to inject a signal charge proportional to a difference between the input reference voltage and the input signal, and the signal charge is sequentially transferred. A
magnitude of the input reference voltage is changed in accordance with a magnitude of a maximum value of the input signal so that transfer of charges which do not contribute to signal component is suppressed and a transfer efficiency is improved.
A charge transfer device has one or more charge injection areas each having an input diffusion layer and two or more input gate electrodes. An input signal is applied to the input diffusion layer, a clock voltage is applied to one of the input gates and an input reference voltage is applied to the other input gate to inject a signal charge proportional to a difference between the input reference voltage and the input signal, and the signal charge is sequentially transferred. A
magnitude of the input reference voltage is changed in accordance with a magnitude of a maximum value of the input signal so that transfer of charges which do not contribute to signal component is suppressed and a transfer efficiency is improved.
Description
.~2~
1 BAC~GROUND OF THE lNv~NlLON
The present in~ention r~l~tes to a ~ignal transfer ~st~m which prave~ts charges which do not cha~ge wit~ time from being i~ected as signal charges in order to pre~ent 3aturation o~ trans~r charges and which is particularly suitable to a tapped, charge ~o~pled..device (C~D).
As i~ well knswu; a CCD has a ~emiconductor ~ubs~rate and electrodes i~sula~ed from the ~ubstrate a~d serially tra~sfers ignal chargos of minority carriers ~tored in pote~tial wells formed in the s~miconductor substrate benea~h ~he electrodes, i~ a loagitl~in~l directi3n of a ~hA~nel by applying a multi-phase voltage to ~he electrodes. It has many 1~ application~ in the field of signal processing such as a delay line for an analog ~ignal~
Two methods for injecting signal charges to the CCD, are the diode cutoff method and the potential balance method which are disclosed in a Japanese version of ~'Charge Transfer Devices" by C.H. Sequin and `
M~F. Tompsett, in Bell Telephone Lab, in U.S.A., published Feb. 20, 1978, pages 42 - 46, However, neither of those methods teaches an efficient way to transfer charges nor suppression of transfer of spurious charges other than signal charges.
1 kUM~L~R~ o~ T~æ ~NV~NllON
It is an object of the present invention to provide a ~ignal transfer sy~tem ha~ing an improved transfer ef~i~iency for changes u~d as ~ignal S c~myo~ents.
In accordance with the present invention there is provided means for shifting the load line of an input signal in accordance with a change of a direct current component ~mean value) or a peak value of an lnput signal waveform applied to a charge transfer device so that a peak of the input signal is held at a level which prevents charges which are not a function of the input signal useless from being injected.
BRIEF DESCRIPTION OF T~ DRA~INGS
Fig. 1 ~hows a circuit diasram of a first Pmho~ime~t of the present invention, Fig. 2 shows waveforms for illustrat~ng phase r~lations among clo~
. Fig. 3 illustxates trans~er of charges, Fig. 4 shows the relationship between an input signal and a. signal actually inputted to a charge transfer device, Fig. S shows a relation between a control voltage and a~ input signal~
Fig. 6 h~ws a circuit diagsam o a ~eoond 2mbo~; m~nt Of ~he present invention, Fig. 7 sh~ws waveforms o~ an inpu~ signal ~2~
and an input clock signal~
Fig~ 8 shows waveforms for illustrating phase relations among clocks, Fig. 9 illustrates transfer of charges, and Fig. 10 shows a circuit~ diagram of a main portion of a third embodiment of the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
Fig. 1 shows a circu.it diagram of one embodi-ment of the present inv.ention. In Fig. l, numeral 1.
denotes a signal sourcel numeral 2 denotes a gate clock source, numeral 10 denotes a p-type silicon substrate, numexal 11 denotes an cxidized silicon layer, numeral 12 denotes an n-type diffusion layer and numerals 13 - 22 denote gate electrodes which are usually made ~f alumin-um or poly-crystalli.ne silicon. The oxidized silicon layer 11 insulates the substrate 10 from the gate electrodes 13 - 220 Vin denotes an input signal voltage applied to the diffusion layer 12, VDD denotes a direct voltage, ~G denotes a gate clock, Vin min denotes an input reference direct bias voltage applied to the gate 14, and ~1 and ~2 denote charge transfer clocks.
The n MOSFET's 51 and S3 and a load resistor 61 form a peak voltage detection circuit 80A, and n-MOSFET's 55 and 57 and a load resistor 63 form a gain control cirCuit 80-The diode cutoff method is first explained. Tothis end, let us assume that the input reference voltage Vin min is not applied to the electrode 14, that is, ~L2~
the electrode 14 is connected to a fixed I
'~
3a -~2~
pc~wer supply of a voltage V~ c.
Fig. 2 shows ~mplitudes ~nd phases o~ ~he c~oc~s 01~ 02 ~nd 0G $hown in Fig. 1. ~i~s, 3(a), 3 ~b), 3 ~c) ~nd 3 td) illu-~ trate an operation ~ e 5 CCD input area shown ~n ~ig. 1. Fig. 3 ~a) is a diagram in the vicinity of a Rubstrate urface of the input area and ~igs. 3~b~ and 3(~) illustra~e poterltials in the substrate beneath th~ ga~e electrodes 13 - 22 and mo~vefrlent of ~harges ~t times tl, t2 ~d t3 shown 10 in ~ig. 2. . ~he input signal is applied to the n~-type diffusior~ layer 12 and the ~ate @lectrode 18 is opened at the time tl by the ga~e clock ~; so that a eharge proportional to the zlmplitu~e o~ input signal is ~illed under the gate elec1:rode 14 to which . . 15 the inpu~ referencP voltage t7c~ is applied. At the t~me t2~ the gate ele~trode 18 is ~losed by ~che g2~e ~locX ~G and a signal charge Qsig is stored in ~
potential well ormed by the gate ~lectrodes 18, 14 ~nd 19. Thi~ signal eharye is transferred ~equentially 20 by ~he tr~nsf erring cloc3cs ~ nd ~2 after ~he ~ime t3 as sh~n in Fig, 3 (d) . The above operation is repeated so ~ha~ s~ snal charges Qsig repre.~enting t~e amplitudes of the input ~ignal ~oltag~s Vin ar sequentially inputted to the CCD. The relationship between an internal potential ~in and the signal charge Qsig is shown in Fig. 4, where ~in is an internal poten-tial under the n-type diffusion layer 12 and ~cc is an 9~
internal potential under the gate electrode 14. When in 7 ~cc the internal potential under the gate I
~.s~
. - 4a -. - ~
~2~ 7 electrode 14 in Fig. 3 (b) ~s smaller t~an the internal potential ~Pin under the n~type di~fusion 'I ayer 12 a~d hence the charge is not filled Imder the gate elec~rode 14 at the time tl. Ac~or~ingly, Qsig ~
~ O Y)in c ~cc ~ Qsig change5 1~ Arly ith spect to Si ~ ~hen ~in ~ S~O ' Qgig than a T~lAXi mllm stored ~arge Qma~c in the po~ential w~ t the trans~er areR of ~he CCD, saturation occ~ars . ~ccordingly 9 in order ~o secu~e a dynamic lO :range,- the inean value of the input 5ig21a~ is set suc~ .
that the internal potential urlder the ~-type diffu~ion layer 12 assumesS~DC shown in Fig. 4.
When a ~ignal ~hown by a broken line in Fig . 4 is t~ansf~rred under ~uch a ~oQdition, Q ' O ~ QO
15 is transferred as a spurious charge. Thus, in a charge tra~sfer devioe like a tapped l:CD delay line in which charges supplied froTn respective taps to a main transfer path are combined in t~e main trans~er path, spurious charges from the respecti~re taps ase com~ined 2D a~d the main transf~r path 3aturates.
AS a result, in the cir :uit of ~ig . 1, the voltage of ~he electrode 14 i5 controlled i~ accordance wi~:h a peak v~lue of the input volkage Vi~ and a load l~ne (~ in Fig . 4 ) is shifted so that the charge 25 ~orrespondi~g to the peak ~alue always ~ ss~ne~s a nimllm charge QO-V'in is an input signal t~ the gain oontrolcir~Uit ~0, V in min i~ a Tn; n;mllm volta.ge o~ the input `t ~lZ~ tJ
1 signal V~in, VcOn is a control voltage to control the gain of the gain control circuit 80 and the gain of the peak voltage detection current 80A, and V10 and V20 are direct voltages. Fig. 5 shows a relation between the output (or input to the CCD) voltage Vin of the gain control circuit 80 and the control voltage VCOn. In Fig. 5, curve 1 shows a waveform of the output voltage Vin when the control voltage VCOn is Vl, curve 2 shows a waveform of the output voltage Vi~l when the control voltage VCOn is V2, and VGl is a maximum voltage of the waveform 1. In the peak voltage detection circuit 80A, the control voltage VCOn is applied to the gate of the n-MOSFET 51 and the minimum voltage V'in min f the input signal V'in is applied to the gate of the n-MOSFET 53.
By selecting the resistance of the resistor 61 to be-equal to that of the resistor 63, the peak voltage detector circuit 80A produces an output voltage which substantially follows a curve designated by the parameter V'in min in Fig. 5. Thus~ the output voltage Vin min is always coincident with the maximum of the output signal Vin of the gain control circuit 80. The bias voltages V10 and V20 are selected such that a difference therebetween is equal to a difference between the potential under the diffusion layer 12 and the potential under the gate electrode 14.
Since the voltage applied to the gate electrode 14 changes in accordance with the peak t~, ~LZ~ 7 1 value of the input voltage Vi~, the load line also changes as shown by L and L'in accordance with the peak value of the input voltage Vin so that the minimum value of the transfer charge is always maintained at QO. From a standpoint of high transfer efficiency, it is desirable that the minimum charge QO is zero, but a cer~ain direct current component is added in order to eliminate an influence by a non-linear portion of a rising region o the load line.
Fig. 6 shows a circuit diagram for the poten-tial balance method. In Fig. 6, numeral 3 den~tes a signal source, numeral 4 denotes a clock source, numeral ÇO denotes a p-type silicon substrate, numeral 61 denotes an oxidized silicon layer, numeral 62 denotes an n~-type diffusion layer, and numerals 163 - 172 denote gate electrodes, which are made of aluminum or poly-crystalline silicon. The oxidized silicon layer 61 insulates the substrate from the gate electrodesO Vin is an input signal voltage, VDD and V'cc and Vc are direct voltages, ~1 and ~2 are charge transfer clocks, SP is a sampling clock and ~'G is a signal charge inputting clock. Numerals 80A' and 80' denote circuits which are similar to the peak voltage detection circuit 80A' and the gain control circuit 80 shown in Fig. 1, and resistors 61 and 63 have the same resistance. Thus, the output voltage of the DC control circuit 80A is equal to min~mum output voltage of the gain control circuit 80'.
1 In a switching circuit 100 comprising n-MOSFET' 6 96 and 97 and a p-MOSFET 98, the n-MOSFET 97 and the p-MOSFET 98 conduct and the n-MOSFET 96 does not conduct when the clock ~'G is at a high level. Thus, a voltage of an output clock ~"G is equal to the output voltage of the peak voltage detection circuit 80A'. On the other hand, when the clock ~'G is at a low level, the n-MOSFET 96 conducts and the n-MOSFET 97 and the p-MOSFET
98 do not conductl and the voltage of the clock ~"G is zero. Accordingly, the waveform of the clock ~"G assumes a waveform shown in Fig. 7.
In order to explain the potential balance method, let us assume tha~ the clock ~'G is applied directly to the gate electrode 69.
Fig. 8 shows amplitudes and phases of the clocks ~ 2~ SP and ~'G shown in Fig. 6. Figs. 9(a), 9(b), 9(c) and 9~d~ illustrate an operation of a charge in~ection area. Fig. 9(a) shows a diagram in the vicin-ity of the substrate surface in the input area shown in Fig. 6 and Figs. 9(b~ - 9(d) show potentials in the sub-strate under the gate electrodes 163 - 172 and the move-ment of the charges at times t'o - t'3 shown in Fig. 8.
At the time t'o, the internal potential under the n -type diffusion layer 62 is at a level shown by a chain line in Fig. 9(b). At the time t'l, the voltage of the samp-ling clock SP changes from VspL to VspH and the internal potential under the n type diffusion l~yer 62 changes to a level shown by a solid line in Fig. 9~b) and a charge .; . .-, ~, -- 8 ~
J
1 representing the magnitude of thQ ~nput signal ~oltage Visl applied ~o ~he gate electrode 6 8 is stored in a pstential well ~orr~d by the gate ~le~:t~ode~ 64, 68 and 69 . 7~t the t:une t;2 ' r t~e ~roltage of the ~ig~al 5 charge inputting clock P~G applied to the gate electrode 6 9 changes from O to VG ~ and a ~ignal charge Qsi which is proport~o~Al to VG ~ Vi is stored ln a potential well formod by the gate ~lec~odes 65, 69 . and 70 as ~hown in Fig. ~ (c~ . Thereaft~r, the signal 10 . ::harg~ Qsig is sequen:tially transferred ~y the transfer cl~:ks ~1 and P'2 as l;hown in Fig. 9 (d) . The ~bove operation is repeated 80 that signal charges Qsig representing the magnitudes of the input signai voltages Vir~ are sequentially in~ec~ed tc~ ~he CCD.
Sin~e the load lin~ show~ in Fig. 4 is shifted by ~e clock vol~age applied to the gate elec~rode 69, w~en the clocl~ P~"G i5 applied ~o the s~ate electrode 69, the load line is shifted in ac~ordance with th~ peak value of the input sigs~al in 20 ~he same manner as ~e previous embodiment ~o $hat the spurious Gharges are no~: inj ec:ted .
If the signal applied to the charge trancfer device has a constant amplitude as~d a varying direct- current component, the spuriQus charge transfer can be reduced 25 by a s:ircui~ shown in Fig. lOr ~ ig. 10 shows a main portion o a third ~mbo~;m~r~t ~f th~ presen~ in~rention. Numeral 150 denotes a pnp tsan~;istor, num~ral 151 denotes a r~
~2~
1 resisto~, numeral 152 denotes a potentiomete~, numeral 153 denotes a capacitor, and numeral 154 de~otes a switch ( a~tually a txansistor because o ~ high drive ~re~lency) which is set ~o a~ upper co~t~ct S whe~ t:he clsc3c 0't; ~hown in Fig" 7 is ~t a high level and ~e~ to a lower cont~ct when it is at a low level.
q~he capacitor 153 ser~res to el;m;n;~te an ~C component of 'che input signal Vi~ ~ and the. potentiomete~ 152 is ~tially ~et ~uch that t~e high le~rel of 'che O output ~ignal Y~G ' o~ th~ .~wit~h; n~ ~i~cuit 154 assumes the voltage satisfying the relationship between the internal potential ~DC and ~cc shown in Fig. 4.
Assume that the high level of the clock ~G is equal to VG when the direct-current component of the input signal voltage Vin is ~in DC Then, the high level of the clock ~G" is smaller than VG when the direct-current component of the input signal voltage Vin is smaller than Vin DC because the base voltage of the trans-istor 150 falls. Accordingly, the high level of the clock ~G actually applied to the gate electrode 169 is proportional to the direct-current component of the input signal voltage ~in.
1 BAC~GROUND OF THE lNv~NlLON
The present in~ention r~l~tes to a ~ignal transfer ~st~m which prave~ts charges which do not cha~ge wit~ time from being i~ected as signal charges in order to pre~ent 3aturation o~ trans~r charges and which is particularly suitable to a tapped, charge ~o~pled..device (C~D).
As i~ well knswu; a CCD has a ~emiconductor ~ubs~rate and electrodes i~sula~ed from the ~ubstrate a~d serially tra~sfers ignal chargos of minority carriers ~tored in pote~tial wells formed in the s~miconductor substrate benea~h ~he electrodes, i~ a loagitl~in~l directi3n of a ~hA~nel by applying a multi-phase voltage to ~he electrodes. It has many 1~ application~ in the field of signal processing such as a delay line for an analog ~ignal~
Two methods for injecting signal charges to the CCD, are the diode cutoff method and the potential balance method which are disclosed in a Japanese version of ~'Charge Transfer Devices" by C.H. Sequin and `
M~F. Tompsett, in Bell Telephone Lab, in U.S.A., published Feb. 20, 1978, pages 42 - 46, However, neither of those methods teaches an efficient way to transfer charges nor suppression of transfer of spurious charges other than signal charges.
1 kUM~L~R~ o~ T~æ ~NV~NllON
It is an object of the present invention to provide a ~ignal transfer sy~tem ha~ing an improved transfer ef~i~iency for changes u~d as ~ignal S c~myo~ents.
In accordance with the present invention there is provided means for shifting the load line of an input signal in accordance with a change of a direct current component ~mean value) or a peak value of an lnput signal waveform applied to a charge transfer device so that a peak of the input signal is held at a level which prevents charges which are not a function of the input signal useless from being injected.
BRIEF DESCRIPTION OF T~ DRA~INGS
Fig. 1 ~hows a circuit diasram of a first Pmho~ime~t of the present invention, Fig. 2 shows waveforms for illustrat~ng phase r~lations among clo~
. Fig. 3 illustxates trans~er of charges, Fig. 4 shows the relationship between an input signal and a. signal actually inputted to a charge transfer device, Fig. S shows a relation between a control voltage and a~ input signal~
Fig. 6 h~ws a circuit diagsam o a ~eoond 2mbo~; m~nt Of ~he present invention, Fig. 7 sh~ws waveforms o~ an inpu~ signal ~2~
and an input clock signal~
Fig~ 8 shows waveforms for illustrating phase relations among clocks, Fig. 9 illustrates transfer of charges, and Fig. 10 shows a circuit~ diagram of a main portion of a third embodiment of the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
Fig. 1 shows a circu.it diagram of one embodi-ment of the present inv.ention. In Fig. l, numeral 1.
denotes a signal sourcel numeral 2 denotes a gate clock source, numeral 10 denotes a p-type silicon substrate, numexal 11 denotes an cxidized silicon layer, numeral 12 denotes an n-type diffusion layer and numerals 13 - 22 denote gate electrodes which are usually made ~f alumin-um or poly-crystalli.ne silicon. The oxidized silicon layer 11 insulates the substrate 10 from the gate electrodes 13 - 220 Vin denotes an input signal voltage applied to the diffusion layer 12, VDD denotes a direct voltage, ~G denotes a gate clock, Vin min denotes an input reference direct bias voltage applied to the gate 14, and ~1 and ~2 denote charge transfer clocks.
The n MOSFET's 51 and S3 and a load resistor 61 form a peak voltage detection circuit 80A, and n-MOSFET's 55 and 57 and a load resistor 63 form a gain control cirCuit 80-The diode cutoff method is first explained. Tothis end, let us assume that the input reference voltage Vin min is not applied to the electrode 14, that is, ~L2~
the electrode 14 is connected to a fixed I
'~
3a -~2~
pc~wer supply of a voltage V~ c.
Fig. 2 shows ~mplitudes ~nd phases o~ ~he c~oc~s 01~ 02 ~nd 0G $hown in Fig. 1. ~i~s, 3(a), 3 ~b), 3 ~c) ~nd 3 td) illu-~ trate an operation ~ e 5 CCD input area shown ~n ~ig. 1. Fig. 3 ~a) is a diagram in the vicinity of a Rubstrate urface of the input area and ~igs. 3~b~ and 3(~) illustra~e poterltials in the substrate beneath th~ ga~e electrodes 13 - 22 and mo~vefrlent of ~harges ~t times tl, t2 ~d t3 shown 10 in ~ig. 2. . ~he input signal is applied to the n~-type diffusior~ layer 12 and the ~ate @lectrode 18 is opened at the time tl by the ga~e clock ~; so that a eharge proportional to the zlmplitu~e o~ input signal is ~illed under the gate elec1:rode 14 to which . . 15 the inpu~ referencP voltage t7c~ is applied. At the t~me t2~ the gate ele~trode 18 is ~losed by ~che g2~e ~locX ~G and a signal charge Qsig is stored in ~
potential well ormed by the gate ~lectrodes 18, 14 ~nd 19. Thi~ signal eharye is transferred ~equentially 20 by ~he tr~nsf erring cloc3cs ~ nd ~2 after ~he ~ime t3 as sh~n in Fig, 3 (d) . The above operation is repeated so ~ha~ s~ snal charges Qsig repre.~enting t~e amplitudes of the input ~ignal ~oltag~s Vin ar sequentially inputted to the CCD. The relationship between an internal potential ~in and the signal charge Qsig is shown in Fig. 4, where ~in is an internal poten-tial under the n-type diffusion layer 12 and ~cc is an 9~
internal potential under the gate electrode 14. When in 7 ~cc the internal potential under the gate I
~.s~
. - 4a -. - ~
~2~ 7 electrode 14 in Fig. 3 (b) ~s smaller t~an the internal potential ~Pin under the n~type di~fusion 'I ayer 12 a~d hence the charge is not filled Imder the gate elec~rode 14 at the time tl. Ac~or~ingly, Qsig ~
~ O Y)in c ~cc ~ Qsig change5 1~ Arly ith spect to Si ~ ~hen ~in ~ S~O ' Qgig than a T~lAXi mllm stored ~arge Qma~c in the po~ential w~ t the trans~er areR of ~he CCD, saturation occ~ars . ~ccordingly 9 in order ~o secu~e a dynamic lO :range,- the inean value of the input 5ig21a~ is set suc~ .
that the internal potential urlder the ~-type diffu~ion layer 12 assumesS~DC shown in Fig. 4.
When a ~ignal ~hown by a broken line in Fig . 4 is t~ansf~rred under ~uch a ~oQdition, Q ' O ~ QO
15 is transferred as a spurious charge. Thus, in a charge tra~sfer devioe like a tapped l:CD delay line in which charges supplied froTn respective taps to a main transfer path are combined in t~e main trans~er path, spurious charges from the respecti~re taps ase com~ined 2D a~d the main transf~r path 3aturates.
AS a result, in the cir :uit of ~ig . 1, the voltage of ~he electrode 14 i5 controlled i~ accordance wi~:h a peak v~lue of the input volkage Vi~ and a load l~ne (~ in Fig . 4 ) is shifted so that the charge 25 ~orrespondi~g to the peak ~alue always ~ ss~ne~s a nimllm charge QO-V'in is an input signal t~ the gain oontrolcir~Uit ~0, V in min i~ a Tn; n;mllm volta.ge o~ the input `t ~lZ~ tJ
1 signal V~in, VcOn is a control voltage to control the gain of the gain control circuit 80 and the gain of the peak voltage detection current 80A, and V10 and V20 are direct voltages. Fig. 5 shows a relation between the output (or input to the CCD) voltage Vin of the gain control circuit 80 and the control voltage VCOn. In Fig. 5, curve 1 shows a waveform of the output voltage Vin when the control voltage VCOn is Vl, curve 2 shows a waveform of the output voltage Vi~l when the control voltage VCOn is V2, and VGl is a maximum voltage of the waveform 1. In the peak voltage detection circuit 80A, the control voltage VCOn is applied to the gate of the n-MOSFET 51 and the minimum voltage V'in min f the input signal V'in is applied to the gate of the n-MOSFET 53.
By selecting the resistance of the resistor 61 to be-equal to that of the resistor 63, the peak voltage detector circuit 80A produces an output voltage which substantially follows a curve designated by the parameter V'in min in Fig. 5. Thus~ the output voltage Vin min is always coincident with the maximum of the output signal Vin of the gain control circuit 80. The bias voltages V10 and V20 are selected such that a difference therebetween is equal to a difference between the potential under the diffusion layer 12 and the potential under the gate electrode 14.
Since the voltage applied to the gate electrode 14 changes in accordance with the peak t~, ~LZ~ 7 1 value of the input voltage Vi~, the load line also changes as shown by L and L'in accordance with the peak value of the input voltage Vin so that the minimum value of the transfer charge is always maintained at QO. From a standpoint of high transfer efficiency, it is desirable that the minimum charge QO is zero, but a cer~ain direct current component is added in order to eliminate an influence by a non-linear portion of a rising region o the load line.
Fig. 6 shows a circuit diagram for the poten-tial balance method. In Fig. 6, numeral 3 den~tes a signal source, numeral 4 denotes a clock source, numeral ÇO denotes a p-type silicon substrate, numeral 61 denotes an oxidized silicon layer, numeral 62 denotes an n~-type diffusion layer, and numerals 163 - 172 denote gate electrodes, which are made of aluminum or poly-crystalline silicon. The oxidized silicon layer 61 insulates the substrate from the gate electrodesO Vin is an input signal voltage, VDD and V'cc and Vc are direct voltages, ~1 and ~2 are charge transfer clocks, SP is a sampling clock and ~'G is a signal charge inputting clock. Numerals 80A' and 80' denote circuits which are similar to the peak voltage detection circuit 80A' and the gain control circuit 80 shown in Fig. 1, and resistors 61 and 63 have the same resistance. Thus, the output voltage of the DC control circuit 80A is equal to min~mum output voltage of the gain control circuit 80'.
1 In a switching circuit 100 comprising n-MOSFET' 6 96 and 97 and a p-MOSFET 98, the n-MOSFET 97 and the p-MOSFET 98 conduct and the n-MOSFET 96 does not conduct when the clock ~'G is at a high level. Thus, a voltage of an output clock ~"G is equal to the output voltage of the peak voltage detection circuit 80A'. On the other hand, when the clock ~'G is at a low level, the n-MOSFET 96 conducts and the n-MOSFET 97 and the p-MOSFET
98 do not conductl and the voltage of the clock ~"G is zero. Accordingly, the waveform of the clock ~"G assumes a waveform shown in Fig. 7.
In order to explain the potential balance method, let us assume tha~ the clock ~'G is applied directly to the gate electrode 69.
Fig. 8 shows amplitudes and phases of the clocks ~ 2~ SP and ~'G shown in Fig. 6. Figs. 9(a), 9(b), 9(c) and 9~d~ illustrate an operation of a charge in~ection area. Fig. 9(a) shows a diagram in the vicin-ity of the substrate surface in the input area shown in Fig. 6 and Figs. 9(b~ - 9(d) show potentials in the sub-strate under the gate electrodes 163 - 172 and the move-ment of the charges at times t'o - t'3 shown in Fig. 8.
At the time t'o, the internal potential under the n -type diffusion layer 62 is at a level shown by a chain line in Fig. 9(b). At the time t'l, the voltage of the samp-ling clock SP changes from VspL to VspH and the internal potential under the n type diffusion l~yer 62 changes to a level shown by a solid line in Fig. 9~b) and a charge .; . .-, ~, -- 8 ~
J
1 representing the magnitude of thQ ~nput signal ~oltage Visl applied ~o ~he gate electrode 6 8 is stored in a pstential well ~orr~d by the gate ~le~:t~ode~ 64, 68 and 69 . 7~t the t:une t;2 ' r t~e ~roltage of the ~ig~al 5 charge inputting clock P~G applied to the gate electrode 6 9 changes from O to VG ~ and a ~ignal charge Qsi which is proport~o~Al to VG ~ Vi is stored ln a potential well formod by the gate ~lec~odes 65, 69 . and 70 as ~hown in Fig. ~ (c~ . Thereaft~r, the signal 10 . ::harg~ Qsig is sequen:tially transferred ~y the transfer cl~:ks ~1 and P'2 as l;hown in Fig. 9 (d) . The ~bove operation is repeated 80 that signal charges Qsig representing the magnitudes of the input signai voltages Vir~ are sequentially in~ec~ed tc~ ~he CCD.
Sin~e the load lin~ show~ in Fig. 4 is shifted by ~e clock vol~age applied to the gate elec~rode 69, w~en the clocl~ P~"G i5 applied ~o the s~ate electrode 69, the load line is shifted in ac~ordance with th~ peak value of the input sigs~al in 20 ~he same manner as ~e previous embodiment ~o $hat the spurious Gharges are no~: inj ec:ted .
If the signal applied to the charge trancfer device has a constant amplitude as~d a varying direct- current component, the spuriQus charge transfer can be reduced 25 by a s:ircui~ shown in Fig. lOr ~ ig. 10 shows a main portion o a third ~mbo~;m~r~t ~f th~ presen~ in~rention. Numeral 150 denotes a pnp tsan~;istor, num~ral 151 denotes a r~
~2~
1 resisto~, numeral 152 denotes a potentiomete~, numeral 153 denotes a capacitor, and numeral 154 de~otes a switch ( a~tually a txansistor because o ~ high drive ~re~lency) which is set ~o a~ upper co~t~ct S whe~ t:he clsc3c 0't; ~hown in Fig" 7 is ~t a high level and ~e~ to a lower cont~ct when it is at a low level.
q~he capacitor 153 ser~res to el;m;n;~te an ~C component of 'che input signal Vi~ ~ and the. potentiomete~ 152 is ~tially ~et ~uch that t~e high le~rel of 'che O output ~ignal Y~G ' o~ th~ .~wit~h; n~ ~i~cuit 154 assumes the voltage satisfying the relationship between the internal potential ~DC and ~cc shown in Fig. 4.
Assume that the high level of the clock ~G is equal to VG when the direct-current component of the input signal voltage Vin is ~in DC Then, the high level of the clock ~G" is smaller than VG when the direct-current component of the input signal voltage Vin is smaller than Vin DC because the base voltage of the trans-istor 150 falls. Accordingly, the high level of the clock ~G actually applied to the gate electrode 169 is proportional to the direct-current component of the input signal voltage ~in.
Claims (12)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A charge transfer system comprising:
a charge transfer device having a semiconductor sub-strate including a diffusion region, a first region adjacent to said diffusion region, a second region adjacent to said first region, and a third region to which charge carriers stored in said second region are transferred, a first electrode disposed above said first region and insulated from said substrate, and a second electrode disposed above said second region and insulated from said substrate, said charge carriers being responsive to a voltage difference between a voltage applied to said diffusion region and a voltage applied to said second electrode when a clock pulse is applied to said first electrode;
a signal source for generating an electrical signal to be charge-transferred;
a clock pulse source for supplying said clock pulse to said first electrode of said charge transfer device;
signal supply means connected between said signal source and said diffusion region of said charge transfer device for controlling an amplitude of a signal applied to said diffusion region; and control means for supplying a bias voltage varying with a change of a peak value of said electrical signal to said second electrode of said charge transfer device so as to maintain a minimum value of said charge carriers corresponding to said peak value of said electrical signal at a relatively constant value.
a charge transfer device having a semiconductor sub-strate including a diffusion region, a first region adjacent to said diffusion region, a second region adjacent to said first region, and a third region to which charge carriers stored in said second region are transferred, a first electrode disposed above said first region and insulated from said substrate, and a second electrode disposed above said second region and insulated from said substrate, said charge carriers being responsive to a voltage difference between a voltage applied to said diffusion region and a voltage applied to said second electrode when a clock pulse is applied to said first electrode;
a signal source for generating an electrical signal to be charge-transferred;
a clock pulse source for supplying said clock pulse to said first electrode of said charge transfer device;
signal supply means connected between said signal source and said diffusion region of said charge transfer device for controlling an amplitude of a signal applied to said diffusion region; and control means for supplying a bias voltage varying with a change of a peak value of said electrical signal to said second electrode of said charge transfer device so as to maintain a minimum value of said charge carriers corresponding to said peak value of said electrical signal at a relatively constant value.
2. A charge transfer system comprising:
a charge transfer device having a semiconductor sub-strate including first region, a second region adjacent to said first region, a third region adjacent to said second region, and a fourth region to which charge carriers stored in said second region are transferred, first, second and third electrodes insulated from said substrate and disposed above said first, second and third regions, respectively, said charge carriers at said second region being responsive to a voltage applied to said first electrode if a voltage applied to said second electrode is constant, and trans-ferred charge carriers from said second region to said fourth region being responsive to a voltage applied to said third electrode;
a signal source for generating an electrical signal;
a direct voltage source for supplying a constant bias voltage to said second electrode;
a clock pulse source for generating a clock pulse for said third electrode of said charge transfer device;
signal supply means connected between said signal source and said first electrode of said charge transfer device for controlling an amplitude of a signal applied to said first electrode; and pulse control means connected to said clock pulse source and said third electrode of said charge transfer device for supplying a clock pulse whose amplitude varies with a change of a peak value of said electrical signal so as to maintain a minimum value of said transferred charge carriers corresponding to said peak value of said electrical signal at a relatively constant value.
a charge transfer device having a semiconductor sub-strate including first region, a second region adjacent to said first region, a third region adjacent to said second region, and a fourth region to which charge carriers stored in said second region are transferred, first, second and third electrodes insulated from said substrate and disposed above said first, second and third regions, respectively, said charge carriers at said second region being responsive to a voltage applied to said first electrode if a voltage applied to said second electrode is constant, and trans-ferred charge carriers from said second region to said fourth region being responsive to a voltage applied to said third electrode;
a signal source for generating an electrical signal;
a direct voltage source for supplying a constant bias voltage to said second electrode;
a clock pulse source for generating a clock pulse for said third electrode of said charge transfer device;
signal supply means connected between said signal source and said first electrode of said charge transfer device for controlling an amplitude of a signal applied to said first electrode; and pulse control means connected to said clock pulse source and said third electrode of said charge transfer device for supplying a clock pulse whose amplitude varies with a change of a peak value of said electrical signal so as to maintain a minimum value of said transferred charge carriers corresponding to said peak value of said electrical signal at a relatively constant value.
3. A charge transfer system comprising:
a charge transfer device having a semiconductor sub-strate including a diffusion region, a first region adjacent to said diffusion region, a second region adjacent to said first region, and a third region to which charge carriers stored in said second region are transferred, a first electrode disposed above said first region and insulated from said substrate, and a second electrode disposed above said second region and insulated from said substrate, said charge carriers being responsive to a voltage difference between a voltage applied to said diffusion region and a voltage applied to said second electrode when a clock pulse is applied to first electrode;
a terminal adapted to be connected to a signal source for generating an electrical signal to be charge-transferred;
a terminal adapted to be connected to a clock pulse source for supplying said clock pulse to said first electrode of said charge transfer device;
signal supply means connected between said terminal adapted to be connected to said signal source and said diffusion region of said charge transfer device for con-trolling an amplitude of a signal applied to said diffusion region; and control means for supplying a bias voltage varying .
with a change of a peak value of said electrical signal to said second electrode of said charge transfer device so as to maintain a minimum value of said charge carriers corresponding to said peak value of said electrical signal at a relatively constant value.
a charge transfer device having a semiconductor sub-strate including a diffusion region, a first region adjacent to said diffusion region, a second region adjacent to said first region, and a third region to which charge carriers stored in said second region are transferred, a first electrode disposed above said first region and insulated from said substrate, and a second electrode disposed above said second region and insulated from said substrate, said charge carriers being responsive to a voltage difference between a voltage applied to said diffusion region and a voltage applied to said second electrode when a clock pulse is applied to first electrode;
a terminal adapted to be connected to a signal source for generating an electrical signal to be charge-transferred;
a terminal adapted to be connected to a clock pulse source for supplying said clock pulse to said first electrode of said charge transfer device;
signal supply means connected between said terminal adapted to be connected to said signal source and said diffusion region of said charge transfer device for con-trolling an amplitude of a signal applied to said diffusion region; and control means for supplying a bias voltage varying .
with a change of a peak value of said electrical signal to said second electrode of said charge transfer device so as to maintain a minimum value of said charge carriers corresponding to said peak value of said electrical signal at a relatively constant value.
4. A charge transfer system according to claim 3 wherein said control means includes first and second gain control units each having first and second input terminals and an output terminal, an output voltage at said output terminal being independently controlled by input voltage applied to said first and second input terminals, said first input terminal of said first gain control unit being said terminal adapted to be connected to the signal source, said output terminal of said first gain control unit being connected to said diffusion layer, said first input terminal and said output terminal of said second gain control unit being connected to a power supply of a voltage equal to a minimum value of said electrical signal and said second gate electrode respectively, and said second input terminals of said first and second gain control units being connected together.
5. A charge transfer system in accordance with claim 4, wherein each of said first and second gain control units includes first and second transistors and a load, said first and second input terminals are connected to control electrodes of said first and second transistors, respectively, and a connection point of said second trans-istor and said load is connected to said output terminal.
6. A charge transfer system comprising:
a charge transfer device having a semiconductor sub-strate including a first region, a second region adjacent to said first region, a third region adjacent to said second region, and a fourth region to which charge carriers stored in said second region are transferred, first, second and third electrodes insulated from said substrate and disposed above said first, second and third regions, respectively, said charge carriers at said second region being responsive to a voltage applied to said first electrode if a voltage applied to said second electrode is constant and transferred charge carriers from said second region to said fourth region being responsive to a voltage applied to said third electrode;
a terminal adapted to be connected to a signal source for generating an electrical signal;
a terminal adapted to be connected to a direct voltage source for supplying a constant bias voltage to said second electrode;
a terminal adapted to be connected to a clock pulse source for generating a clock pulse for said third elec-trode of said charge transfer device;
signal supply means connected between said terminal adapted to be connected to said signal source and said first electrode of said charge transfer device for control-ling an amplitude of a signal applied to said first electrode; and pulse control means connected to said terminal adapted to be connected to said clock pulse source and said third electrode of said charge transfer device for supplying a clock pulse whose amplitude varies with a change of a peak value of said electrical signal so as to maintain a minimum value of said transfer charge carriers corresponding to said peak value of said electrical signal at a relatively constant value.
a charge transfer device having a semiconductor sub-strate including a first region, a second region adjacent to said first region, a third region adjacent to said second region, and a fourth region to which charge carriers stored in said second region are transferred, first, second and third electrodes insulated from said substrate and disposed above said first, second and third regions, respectively, said charge carriers at said second region being responsive to a voltage applied to said first electrode if a voltage applied to said second electrode is constant and transferred charge carriers from said second region to said fourth region being responsive to a voltage applied to said third electrode;
a terminal adapted to be connected to a signal source for generating an electrical signal;
a terminal adapted to be connected to a direct voltage source for supplying a constant bias voltage to said second electrode;
a terminal adapted to be connected to a clock pulse source for generating a clock pulse for said third elec-trode of said charge transfer device;
signal supply means connected between said terminal adapted to be connected to said signal source and said first electrode of said charge transfer device for control-ling an amplitude of a signal applied to said first electrode; and pulse control means connected to said terminal adapted to be connected to said clock pulse source and said third electrode of said charge transfer device for supplying a clock pulse whose amplitude varies with a change of a peak value of said electrical signal so as to maintain a minimum value of said transfer charge carriers corresponding to said peak value of said electrical signal at a relatively constant value.
7. A charge transfer system according to claim 6, wherein said potential at said predetermined portion of said electrical signal is a peak value of said electrical signal.
8. A charge transfer system according to claim 6, wherein said potential at said predetermined portion of said electrical signal is a mean value of said electrical signal.
9. A charge transfer system according to claim 1 wherein said control means includes first and second gain control units each having first and second input terminals and an output terminal, an output voltage at said output terminal being independently controlled by input voltages applied to said first and second input terminals, said first input terminal and said output terminal of said first gain control unit being connected to said signal source and said diffusion layer, respectively, said first input terminal and said output terminal of said second gain control unit being connected to a power supply of a voltage equal to a minimum value of said electrical signal and said second gate electrode, respectively, and said second input termin-als of said first and second gain control units being connected together.
10. A charge transfer system according to claim 9 wherein each of said first and second gain control units includes first and second transistors and a load, said first and second input terminals are connected to control electrodes of said first and second transistors, respective-ly, and a connection point of said second transistor and said load is connected to said output terminal.
11. A charge transfer system according to claim 2 wherein said potential at said predetermined portion of said electrical signal is a peak value of said electrical signal.
12. A charge transfer system according to claim 2 wherein said potential at said predetermined portion of said electrical signal is a mean value of said electrical signal.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP160972/82 | 1982-09-17 | ||
| JP16097282A JPS5950560A (en) | 1982-09-17 | 1982-09-17 | Charge transfer device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1210097A true CA1210097A (en) | 1986-08-19 |
Family
ID=15726133
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000436571A Expired CA1210097A (en) | 1982-09-17 | 1983-09-13 | Signal transfer system using a charge transfer device |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPS5950560A (en) |
| CA (1) | CA1210097A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60193604A (en) * | 1984-03-16 | 1985-10-02 | 凸版印刷株式会社 | Method and device for manufacturing pottery |
| JP3297946B2 (en) * | 1993-03-23 | 2002-07-02 | ソニー株式会社 | Charge transfer device |
| JP3318905B2 (en) * | 1993-12-03 | 2002-08-26 | ソニー株式会社 | Charge transfer device |
-
1982
- 1982-09-17 JP JP16097282A patent/JPS5950560A/en active Pending
-
1983
- 1983-09-13 CA CA000436571A patent/CA1210097A/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5950560A (en) | 1984-03-23 |
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