JPS60114035A - A/d converter - Google Patents

Abstract

PURPOSE:To attain simplicity of the circuit and integration of the circuit by using a charge transfer element so as to use a voltage comparator with a simple constitution. CONSTITUTION:A reference voltage VREF is divided into 8 ways of voltages by a voltage dividing circuit and outputted in a 3-bit (bit) A/D converter. Resistors each having a resistance value R and resistors each having a resistance value of R/2 are connected in series in the voltage dividing circuit 1 and an output voltage from the n-th connecting point is set so as to form VREFX(2n-1)/16. When an input signal voltage VSIG is zero, since the relation of the 1st and 2nd gate electrodes 18, 19 is VG1>VG2 in all charge injection sections 2-9, no electric charge is injected to all the electric charge injection sections 2-9. Since no electric charge is transferred to an electric charge detecting electrode 13 over 8 times transfer cycles, an output of an output amplifier 14 is ''00000000'', a binary data ''000'' is latched to a data latch circuit 15. Thus, an input signal voltage is converted into a digital quantity of, e.g., VREF/8 steps and the 3-bit A/D conversion is conducted.

Description

[Detailed description of the invention] The present invention relates to an A/D conversion device.

Regarding A/D conversion devices, various systems have been proposed and put into practical use, but it has not been possible to avoid the complexity of the circuit. - An object of the present invention is to provide an A/D conversion circuit that has a simplified circuit and is suitable for integration.

By using a charge transfer element, the present invention can provide a new A/D conversion device that can use a voltage comparator with a simple configuration and is suitable for circuit simplification and integration.

Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 1 shows an embodiment according to the present invention, especially 3 pins)
(bit) This shows an A/D conversion device. Hereinafter, FIG. 1 will be explained in detail.

The reference voltage V □ is divided into 8 ways, 011
It is divided into pressure and output. The voltage divider circuit 1 has a resistance value R
and a resistor with a resistance value R/2 are connected in series, and the output voltage from the n-th connection point is as follows. The eight charge injection units 2 to 9 arranged in parallel are constructed using charge-coupled devices, and each includes a charge injection diode 17 with opposite conductivity types formed on the semiconductor substrate and an insulating film formed on the semiconductor substrate. It is constituted by first and second gate electrodes and electrodes 18 and 19 with electrode metal provided therebetween. The first gate electrodes 18 of each charge injection section are connected to the output of the voltage dividing circuit 1 in sequence. The charge injection diode 17 receives a charge injection pulse S, and the second gate electrode 19 receives an input signal voltage V s
1G are connected to each other. Therefore, the potential under the first gate electrode 18 changes sequentially so that the potential is lowest at the charge injection part 9 and highest at the charge injection part 2. On the other hand, a potential corresponding to the input signal v8□0 is formed under the second gate electrode 19. Therefore, the charge is transferred from the charge injection diode 17 to the second gate electrode 9 through the first gate electrode 18 in response to the charge injection pulse S, but this transfer is smaller than the input signal VglG. Potential constriction 1st
It is limited to the portion provided to the gate electrode 18.

The charges injected under the second gate electrode 19 by the charge injection sections 2 to 9 are transferred by the transfer gate electrode 10.11 to the serial transfer section 12, which is composed of seven charge transfer stages. The serial transfer section 12 is formed of a charge-coupled device, and the serial transfer section 12 is connected to a φ3. φ goose.

Due to the three-phase transfer lock of φ, charges are sequentially transferred to charge detection chamber 4#! Charge transfer of all stages is completed in 08 transfer cycles transferred to X3. The charge detection electrode 13 is formed by a floating diffusion layer, and the amount of charge is converted into a voltage and inputted to the output amplifier 14, and the clock φ is used to
Reset periodically.

The output of the output amplifier 14 is configured such that when a charge is transferred to the charge detection electrode 13, a logic 11'' is output, and when no charge is transferred, a logic 10'' is output. ) is detected by the data latch circuit 15. This detection is performed depending on how many times the number of clocks from the clock control circuit 16 changes. Depending on the detected number of clocks, the data latch circuit forms a binary number and latches it once.

The clock control circuit 16 receives the lock signal φ1. as shown in FIG. φ1. φ3. It generates φ, ', φ, ' and St, and also counts the transfer cycles of the four transfer blocks φ1 to φ3 supplied to the serial transfer section 12 in binary, and outputs the counted data to the data latch circuit 15.

As shown in FIG. 3, the charge injected into the charge injection parts 2 to 9 is determined by the difference in depth between the potential wells formed under the first and second gate m poles 18°19.
That is, the field umbrella using N-type CCD, the first gate 1! The voltage of the pole 18 is va3, and the voltage of the second gate electrode 19 is V.

As shown in FIG. 3, if ≧V, the potential well under the first gate electrode 18 is 2V, then the potential under the first gate electrode 18 is The potential well below the second gate electrode 19 becomes deep, and charges are injected into the potential well below the second gate electrode 19.

Now, assuming that the input signal voltage v8□0 is Vs,, = O, the relationship between the first and second gate electrodes 18, 19 in all charge injection parts 2 to 9 is vo, > va.
.

Therefore, no charge is injected into any of the charge injection sections 2 to 9. Therefore, since no charge is transferred to the charge detection type 4iji 13 for eight transfer cycles, the output of the output amplifier 14 is "oooooooo", and the data latch circuit 15 has binary data (4-2-1 code). ) “000” is latched.

Up to part 5 is V. □>Vo, V from charge input section 6 to charge input section 9. ,〈v6, so electric! No charges are injected into the load input sections 2-5, while charges are injected into the charge input sections 6-9. Therefore, charge is transferred to the charge detection electrode 13 during four transfer cycles;
Charge is not transferred in the fifth and subsequent transfer cycles. Therefore, the output of the output amplifier 14 is "11110000"
Meanwhile, the data latch circuit 15 latches up to the fifth transfer cycle count data @100''.

In this way, in this embodiment, the input signal voltage Fi
' It is converted into a digital quantity of xvw steps, and 3-bit A/D conversion is performed.

In the above explanation, the voltage divider circuit 1 is connected to the first gate electric bucket ts.
The input signal voltage v8, is applied to the second gate voltage &19. However, the relationship between these two gate electrodes 18 and 19 is reversed.

The counting data may be latched at the time when the logic of the output amplifier 14 changes from 11'' to @0#.
, the first gate) is the pole 1 BK is the base f@voltage vIItF
is applied after being divided by the voltage dividing circuit 1, but the charge injection section 2~
By arranging the gate electrodes 9 at equal intervals and using a high resistance polysilicon wiring for the first gate electrode 18, it is also possible to provide a function equivalent to a voltage dividing circuit.

Furthermore, although the above explanation has been made regarding 3-bit A/D conversion, it is generally easy to extend this to n-bit A/D conversion. In this case, the voltage divider circuit 1 has two output voltages, and the m-th voltage is the three-phase C
Although a CD is used, it is also possible to use a two-phase CCD.

As explained above, according to the present invention, there is no need to use a complicated voltage comparison circuit or a sample hold circuit in the conventional method, so the circuit is simplified and an A
The 0 conversion speed that the /D conversion device can achieve is also 1 to 100 μS.
It is possible to achieve relatively high speed, and the effect is great.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the present invention, and FIG. 2 is a diagram showing an embodiment of the present invention. FIG. 1 is a diagram showing the timing in the embodiment, and FIG. 3 is an explanatory diagram of the operation of the charge injection section. 1...Voltage dividing circuit, 2-9...Charge injection part, 10°11...Transfer gate electrode, 12...
...Series charge transfer unit, 13...Charge detection electrode, 14...Output amplifier, 15...Data latch circuit, 16...Clock Control circuit% 17...Charge injection diode, 18...
...first gate electrode, 19...second gate electrode.

Claims (4)

[Claims] (1) A voltage divider circuit that divides a reference voltage to generate a plurality of divided voltages, a plurality of voltage comparators that compare the input signal voltage with each of the plurality of divided voltages, and an output of each voltage comparator. In the A/D conversion device, the plurality of voltage comparators are formed on a semiconductor substrate, and each of the plurality of voltage comparators is formed on a charge injection device formed on the semiconductor substrate. a first gate electrode formed on the semiconductor substrate via an insulating film and to which the divided voltage is supplied; and a second gate electrode formed on the semiconductor substrate via an insulating film and to which the input signal voltage is supplied. game)k
An A/D conversion device characterized by having a pole. (2) A means for obtaining the digital signal, a shift register having a plurality of input terminals to which the outputs of the plurality of voltage and voltage comparators are supplied, and a data input terminal connected to the output terminal of the shift register. An A/D converter N according to claim 1, characterized in that it includes a detector and a circuit that converts the output of the data detector into a digital signal. (3) The A/D conversion device according to claim (2), wherein the shift register is constructed using a charge transfer element. (4) The voltage dividing circuit uses high-resistance polysilicon wiring.
Or the A/D conversion device described in (3).