JPS5575236A - Method of fabricating semiconductor device - Google Patents

Method of fabricating semiconductor device

Info

Publication number
JPS5575236A
JPS5575236A JP15032678A JP15032678A JPS5575236A JP S5575236 A JPS5575236 A JP S5575236A JP 15032678 A JP15032678 A JP 15032678A JP 15032678 A JP15032678 A JP 15032678A JP S5575236 A JPS5575236 A JP S5575236A
Authority
JP
Japan
Prior art keywords
wafer
grooves
semiconductor
recess
urged
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15032678A
Other languages
Japanese (ja)
Inventor
Masao Ishii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP15032678A priority Critical patent/JPS5575236A/en
Publication of JPS5575236A publication Critical patent/JPS5575236A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To improve the yield of fabricating a semiconductor device at its dicing process by chemically etching in advance along the scribe surface of a semiconductor wafer to thereby form a recess groove therealong and forming mechanically a polishing groove therealong.
CONSTITUTION: A resist mask is formed on a semiconductor wafer, and the wafer is etched with a mixture solution of fluoric acid and nitric acid to thereby form lattice recess grooves on the scribe surface thereof. The interval and width of the grooves are selected according to the size of the semiconductor divece. After the recess grooves are diced by a dicing saw to approx. half the thickness of the wafer in depth, the wafer is urged from the opposite side of the grooves to thereby separate it into pieces. When an adhesive tape is labeled on one surface of the wafer at this time and the wafer is then urged on a rubber plate, the array of the wafer can be retained as it is. According to this method, it can eliminate cracks, defects at the edges of the wafer due to the friction among the pieces of the wafer.
COPYRIGHT: (C)1980,JPO&Japio
JP15032678A 1978-12-04 1978-12-04 Method of fabricating semiconductor device Pending JPS5575236A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15032678A JPS5575236A (en) 1978-12-04 1978-12-04 Method of fabricating semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15032678A JPS5575236A (en) 1978-12-04 1978-12-04 Method of fabricating semiconductor device

Publications (1)

Publication Number Publication Date
JPS5575236A true JPS5575236A (en) 1980-06-06

Family

ID=15494564

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15032678A Pending JPS5575236A (en) 1978-12-04 1978-12-04 Method of fabricating semiconductor device

Country Status (1)

Country Link
JP (1) JPS5575236A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6432635A (en) * 1987-07-22 1989-02-02 Alps Electric Co Ltd Manufacture of thin-film element substrate
US4904610A (en) * 1988-01-27 1990-02-27 General Instrument Corporation Wafer level process for fabricating passivated semiconductor devices

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6432635A (en) * 1987-07-22 1989-02-02 Alps Electric Co Ltd Manufacture of thin-film element substrate
US4904610A (en) * 1988-01-27 1990-02-27 General Instrument Corporation Wafer level process for fabricating passivated semiconductor devices

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