JPS5558566A - Semiconductor integrated circuit and semiconductor device - Google Patents

Semiconductor integrated circuit and semiconductor device

Info

Publication number
JPS5558566A
JPS5558566A JP13179978A JP13179978A JPS5558566A JP S5558566 A JPS5558566 A JP S5558566A JP 13179978 A JP13179978 A JP 13179978A JP 13179978 A JP13179978 A JP 13179978A JP S5558566 A JPS5558566 A JP S5558566A
Authority
JP
Japan
Prior art keywords
layer
sit
channel
led
layers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13179978A
Other languages
Japanese (ja)
Inventor
Junichi Nishizawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Research Foundation
Original Assignee
Semiconductor Research Foundation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Research Foundation filed Critical Semiconductor Research Foundation
Priority to JP13179978A priority Critical patent/JPS5558566A/en
Publication of JPS5558566A publication Critical patent/JPS5558566A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To operate signal transmission between chips by light, by providing a photoelectric converter element in a part of the input/output of a semiconductor chip including IC.
CONSTITUTION: After n--layer 2 and n+ surface layer have been grown on n+ base plate 1, p+-layers 3, 4 are formed by selective diffusion. These layers and their concentrations are: n+-layer, 1017∼1020cm-3; n--layer, 1013∼1016cm-3; and p+- layer, 1017∼1020cm-3. The injector is connected with pnp bipolar transistor, the inverter is connected with n channel electrostatic induction transistor SIT, and the output terminal is connected with p+n-n+ LED. The concentration of SIT channel is selected, the channel is completely pinched off by the diffusion potential between the gate channels, and thereby a high potential barrier is formed. In SIT, when the gate is at a low level, the drain assumes a high level, and light is emitted by LED and is let to the input terminal of the other chip by optical fiber 9.
COPYRIGHT: (C)1980,JPO&Japio
JP13179978A 1978-10-25 1978-10-25 Semiconductor integrated circuit and semiconductor device Pending JPS5558566A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13179978A JPS5558566A (en) 1978-10-25 1978-10-25 Semiconductor integrated circuit and semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13179978A JPS5558566A (en) 1978-10-25 1978-10-25 Semiconductor integrated circuit and semiconductor device

Publications (1)

Publication Number Publication Date
JPS5558566A true JPS5558566A (en) 1980-05-01

Family

ID=15066377

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13179978A Pending JPS5558566A (en) 1978-10-25 1978-10-25 Semiconductor integrated circuit and semiconductor device

Country Status (1)

Country Link
JP (1) JPS5558566A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58216460A (en) * 1982-06-09 1983-12-16 Fujitsu Ltd Light integrated circuit device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58216460A (en) * 1982-06-09 1983-12-16 Fujitsu Ltd Light integrated circuit device

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