JPS54132183A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS54132183A JPS54132183A JP4091078A JP4091078A JPS54132183A JP S54132183 A JPS54132183 A JP S54132183A JP 4091078 A JP4091078 A JP 4091078A JP 4091078 A JP4091078 A JP 4091078A JP S54132183 A JPS54132183 A JP S54132183A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- type
- depth
- transistor
- conversion element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Light Receiving Elements (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
PURPOSE: To enhance the operation characteristics of the device by setting the depth of the buried layer where the conversion element is to be provided larger than the depth of the buried layer where the IC element is to be provided when both the IC element and the photoelectric conversion element are provided on each buried layer within the same chip.
CONSTITUTION: N-type buried layer 11 and 12 are formed by diffusion on the surface of P-type Si substrate 10 in opposition to the IC element and the photoelectric conversion element to be provided later. In this case, the depth of layer 11 corresponding to the IC element such as the diode, transistor, etc. is set to several μm ∼ several tens of μm; while the depth of layer 12 corresponding to the photoelectric conversion element such as the photo diode, photo transistor, etc. is set to about 50μm (deeper than layer 12). After this, N-type layer 13 is epitaxial-grown on the entire surface to form P+-type isolation region 14 by diffusion. Then N-type impurity is diffused within island region 15 on layer 11 enclosed by region 14 with the diode, transistor, etc. provided. At the same time, P- or N-type impurity is diffused to island 15' on layer 12 to form the photo diode or photo transistor. Thus, the illumination light can be utilized effectively.
COPYRIGHT: (C)1979,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP53040910A JPS5812744B2 (en) | 1978-04-06 | 1978-04-06 | semiconductor equipment |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP53040910A JPS5812744B2 (en) | 1978-04-06 | 1978-04-06 | semiconductor equipment |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS54132183A true JPS54132183A (en) | 1979-10-13 |
JPS5812744B2 JPS5812744B2 (en) | 1983-03-10 |
Family
ID=12593655
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP53040910A Expired JPS5812744B2 (en) | 1978-04-06 | 1978-04-06 | semiconductor equipment |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5812744B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5041392A (en) * | 1984-10-18 | 1991-08-20 | Matsushita Electronics Corporation | Method for making solid state image sensing device |
-
1978
- 1978-04-06 JP JP53040910A patent/JPS5812744B2/en not_active Expired
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5041392A (en) * | 1984-10-18 | 1991-08-20 | Matsushita Electronics Corporation | Method for making solid state image sensing device |
Also Published As
Publication number | Publication date |
---|---|
JPS5812744B2 (en) | 1983-03-10 |
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