JPS5812744B2 - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPS5812744B2 JPS5812744B2 JP53040910A JP4091078A JPS5812744B2 JP S5812744 B2 JPS5812744 B2 JP S5812744B2 JP 53040910 A JP53040910 A JP 53040910A JP 4091078 A JP4091078 A JP 4091078A JP S5812744 B2 JPS5812744 B2 JP S5812744B2
- Authority
- JP
- Japan
- Prior art keywords
- photoelectric conversion
- conversion element
- buried layer
- light
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Light Receiving Elements (AREA)
- Solid State Image Pick-Up Elements (AREA)
Description
【発明の詳細な説明】
本発明は、IC工程を経て製作される光電変換素子を備
えた半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device including a photoelectric conversion element manufactured through an IC process.
半導体装置が各種の電子機器に利用されるに伴って、ダ
イオード、トランジスタ等からなる従来公知のIC回路
要素に加えて、光に感応して電気信号を出力するホトト
ランジスタ或いはホトダイオード等を同一半導体チップ
内に組み込んで構成し、光信号に応答する機能を備えた
半導体装置が実用に供されている。As semiconductor devices are used in a variety of electronic devices, in addition to conventionally known IC circuit elements such as diodes and transistors, phototransistors or photodiodes that output electrical signals in response to light have been integrated into the same semiconductor chip. Semiconductor devices have been put into practical use, and have a function of responding to optical signals.
上記この種の半導体装置は、従来公知のIC製造技術を
経て製作されるもので、第1図に示す如くP型シリコン
基板1に、後の工程でIC回路要素及び光電変換素子を
組み込むべき領域に対応する領域にN十埋込層2,2′
を予め形成し、その上にN型エビタキシャル層3を成長
させ、上記埋込12,2’上のエビタキシャル層3に不
純物を所望のパターンで拡散してトランジスタ、ダイオ
ード等のIC回路要素Trを形成すると共に、同一チッ
プ内にホトダイオード等の光電変換素子PDを製作して
いる。This type of semiconductor device is manufactured using conventionally known IC manufacturing technology, and as shown in FIG. N0 buried layers 2, 2' in the area corresponding to
is formed in advance, an N-type epitaxial layer 3 is grown thereon, and impurities are diffused into the epitaxial layer 3 on the embeddings 12 and 2' in a desired pattern to form IC circuit elements Tr such as transistors and diodes. At the same time, a photoelectric conversion element PD such as a photodiode is manufactured within the same chip.
上記構造の半導体装置において、光電変換素子領域PD
に光が照射されると光エネルギによってシリコン半導体
内に電子一正孔の対が発生し、これ等夫々が光電変換素
子内のN領域及びP領域に移動することによって出力が
導出される(図中●:電子、○:正孔)。In the semiconductor device having the above structure, the photoelectric conversion element region PD
When irradiated with light, the light energy generates pairs of electrons and holes in the silicon semiconductor, and these move to the N region and P region within the photoelectric conversion element, resulting in output (Fig. (●: electron, ○: hole).
処が動作状態における上記半導体装置は、エビタキシャ
ル成長層(コレクタ)と基板との間が通常逆バイアスさ
れており、エビタキシャル層で吸収した光エネルギによ
って生じた電子一正孔対の内、基板1に近い部分で生じ
た対はコレクタ・基板間に流れる結果となり、光電変換
素子出力としては導出できず装置の機能が達成できない
不都合がある。However, in the above-mentioned semiconductor device in the operating state, the space between the epitaxial growth layer (collector) and the substrate is normally reverse biased, and among the electron-hole pairs generated by the optical energy absorbed by the epitaxial layer, the substrate A pair generated in a portion close to 1 results in a flow between the collector and the substrate, and cannot be derived as a photoelectric conversion element output, resulting in the inconvenience that the function of the device cannot be achieved.
特に光源としてGaAsのような比較的長波長側に発光
強度を有する発光素子に対しては、受光感度が著しく低
下する欠点がある。In particular, a light-emitting element such as GaAs as a light source that has an emission intensity on the relatively long wavelength side has the disadvantage that the light-receiving sensitivity is significantly reduced.
即ち、長波長光ほど半導体表面から深い領域に浸入して
吸収される特性があり、逆バイアスされたPN接合によ
り近い部分で電子一正孔対を生じ、逆バイアスに影響さ
れて出力として取り出せないことになる。In other words, the longer wavelength light has the characteristic that it penetrates deeper into the semiconductor surface and is absorbed, and electron-hole pairs are generated near the reverse biased PN junction, and cannot be extracted as output due to the influence of the reverse bias. It turns out.
上記のような問題に対してエビタキシャル成長層を厚く
する改善策も考えられるが、エビタキシャル成長層を厚
くした場合には同一チップ内に組み込んだIC回路要素
間における絶縁分離機能が効率よ《果されない問題があ
り、エビタキシャル層の厚さとしては15μ程度が限度
となっている。A possible solution to the above problem is to make the epitaxial growth layer thicker, but if the epitaxial growth layer is made thicker, the insulation isolation function between IC circuit elements incorporated in the same chip becomes more efficient. There are unresolved problems, and the maximum thickness of the epitaxial layer is about 15 μm.
また受光感度の低下を受光面積の拡大によって補うこと
も考えられるが、装置の大型化を招《ことになり好まし
《ない。It is also possible to compensate for the decrease in light-receiving sensitivity by increasing the light-receiving area, but this is not preferred as it would lead to an increase in the size of the device.
本発明は上記従来装置における問題点に鑑みてなされた
もので、簡単な構成を付加するのみで光電変換素子の長
波長感度特性の向上を図ることができる半導体装置を提
供するものである。The present invention has been made in view of the above-mentioned problems with the conventional device, and it is an object of the present invention to provide a semiconductor device that can improve the long wavelength sensitivity characteristics of a photoelectric conversion element by simply adding a simple configuration.
以下に図面を用いて本発明を詳細に説明する。The present invention will be explained in detail below using the drawings.
第2図に於て、10はP型導電性を示すシリコン半導体
基板で、該基板10の主表面には、後述する工程によっ
てIC回路要素及び光電変換素子が対応する領域にN型
不純物を高濃度に拡散させたN型埋込層11,12が設
けられている。In FIG. 2, reference numeral 10 denotes a silicon semiconductor substrate exhibiting P-type conductivity, and the main surface of the substrate 10 is highly doped with N-type impurities in regions corresponding to IC circuit elements and photoelectric conversion elements by a process described later. N-type buried layers 11 and 12 are provided which are diffused in concentration.
ここでダイオード、トランジスタ等のIC回路要素が対
応する埋込層11ぱ従来装置と同程度の深さ(数μ〜士
数μ)に設けられているのに対して、ホトダイオード、
ホトトランジスタ等の光電変換素子が対応する埋込層1
2は拡散深さが数十μ(50μ程度)に深く設けられて
いる。Here, while the buried layer 11 corresponding to IC circuit elements such as diodes and transistors is provided at a depth (several microns to several microns) similar to that of conventional devices, photodiodes,
Buried layer 1 corresponding to photoelectric conversion elements such as phototransistors
No. 2 is provided with a deep diffusion depth of several tens of microns (approximately 50 microns).
即ち光電変換素子部において埋込層12と基板10との
pN接合底面が主表面よりより離れて位置する状態に設
けられる。That is, in the photoelectric conversion element portion, the bottom surface of the pN junction between the buried layer 12 and the substrate 10 is located further away from the main surface.
上記各埋込層11,12の作製においては、予め埋込層
12に対応する領域にまず不純物を拡散して充分深く浸
透させ、次に埋込層12をマスクして埋込層11に対応
する領域に浅く不純物を拡散させることによって得られ
る。In the production of each of the buried layers 11 and 12, impurities are first diffused into the region corresponding to the buried layer 12 to penetrate sufficiently deeply, and then the buried layer 12 is masked to form a region corresponding to the buried layer 11. This is obtained by shallowly diffusing impurities into the region where the
しかも埋込層12については、光エネルギーによって生
じた電子一正孔対のライフタイムを長くして少数キャリ
アの寿命の改善を図るため、表面濃度が低くなるような
不純物(例えば拡散係数の大きいリン)及び拡散処理条
件が選ぶことが望ましい。Furthermore, in order to improve the lifetime of minority carriers by increasing the lifetime of electron-hole pairs generated by light energy, the buried layer 12 is made with impurities that lower the surface concentration (for example, phosphorus with a large diffusion coefficient). ) and diffusion treatment conditions are preferably selected.
上記両N型埋込層11,12が拡散された基板10上に
N型エピタキシャル成長層13が形成され、該エビタキ
シャル成長層13に予定されている各IC回路要素及び
光電変換素子間を電気的に分離するためのP十分離領域
14,14・・・・・・が設けられる。An N-type epitaxial growth layer 13 is formed on the substrate 10 in which both of the N-type buried layers 11 and 12 are diffused, and electrical connection is established between each IC circuit element and photoelectric conversion element planned for the epitaxial growth layer 13. P-sufficiently separated regions 14, 14, . . . for separation are provided.
該P+分離領域14で囲まれたN型島領域15にP及び
N不純物が拡散されてダイオード、トランジスタが形成
され、同時に上記深い埋込層12上に位置するN型島領
域15′に、所望の受光感度特性が得られる形状にP及
びN不純物が拡散されてホトダイオード或いはホトトラ
ンジスタ等の光電変換素子が形成される。P and N impurities are diffused into the N-type island region 15 surrounded by the P+ isolation region 14 to form a diode and a transistor, and at the same time, desired A photoelectric conversion element such as a photodiode or a phototransistor is formed by diffusing P and N impurities into a shape that provides light-receiving sensitivity characteristics.
上記構造の半導体装置においては、光電変換素子が組み
込まれる領域の埋込層が予めより深く形成されているた
め、長波長の光エネルギによって生じた電子一正孔対で
あってもコレクター基板間のPN接合に吸収される程度
は従来装置に比して著しく減少し、従って照射光を有効
て光電変換させることができ、装置の動作特性を向上さ
せることができる。In the semiconductor device having the above structure, since the buried layer in the region where the photoelectric conversion element is installed is formed deeper in advance, even if an electron-hole pair generated by long wavelength light energy is generated between the collector substrate The degree of absorption by the PN junction is significantly reduced compared to conventional devices, and therefore the irradiated light can be effectively photoelectrically converted, and the operating characteristics of the device can be improved.
また光電変換効率が向上するため、従来装置と同程度の
出力を得る場合にも、光電変換素子の受光領域の面積を
減少させることができ装置の小型化、低廉化を図ること
ができる。Furthermore, since the photoelectric conversion efficiency is improved, the area of the light-receiving region of the photoelectric conversion element can be reduced even when obtaining the same output as a conventional device, and the device can be made smaller and less expensive.
第1図は従来装置の要部断面図、第2図は本発明による
一実施例の要部断面図である。
10・・・・・・半導体基板、11,12・・・・・・
N型埋込層、13・・・・・・エビタキシャル成長層、
14・・・・・・絶縁分離領域、15・・・・・・IC
回路要素、15′・・・・・・光電変換素子。FIG. 1 is a sectional view of a main part of a conventional device, and FIG. 2 is a sectional view of a main part of an embodiment according to the present invention. 10... Semiconductor substrate, 11, 12...
N-type buried layer, 13...Ebitaxial growth layer,
14...Insulating isolation region, 15...IC
Circuit element, 15'...Photoelectric conversion element.
Claims (1)
変換素子とを、同一チップ内の各埋込層上に設けてなる
半導体装置において、光電変換素子が設けられる埋込層
の深さを、IC回路要素が設けられる埋込層より充分深
く形成したことを特徴とする半導体装置。1. In a semiconductor device in which an IC circuit element such as a diode or a transistor and a photoelectric conversion element are provided on each buried layer in the same chip, the depth of the buried layer in which the photoelectric conversion element is provided is determined by the depth of the IC circuit element. 1. A semiconductor device characterized in that the semiconductor device is formed sufficiently deeper than a buried layer in which a buried layer is provided.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP53040910A JPS5812744B2 (en) | 1978-04-06 | 1978-04-06 | semiconductor equipment |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP53040910A JPS5812744B2 (en) | 1978-04-06 | 1978-04-06 | semiconductor equipment |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS54132183A JPS54132183A (en) | 1979-10-13 |
JPS5812744B2 true JPS5812744B2 (en) | 1983-03-10 |
Family
ID=12593655
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP53040910A Expired JPS5812744B2 (en) | 1978-04-06 | 1978-04-06 | semiconductor equipment |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5812744B2 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3586452T2 (en) * | 1984-10-18 | 1993-03-18 | Matsushita Electronics Corp | SOLID IMAGE SENSOR AND METHOD FOR THE PRODUCTION THEREOF. |
-
1978
- 1978-04-06 JP JP53040910A patent/JPS5812744B2/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS54132183A (en) | 1979-10-13 |
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