JPS58216460A - Light integrated circuit device - Google Patents

Light integrated circuit device

Info

Publication number
JPS58216460A
JPS58216460A JP57099595A JP9959582A JPS58216460A JP S58216460 A JPS58216460 A JP S58216460A JP 57099595 A JP57099595 A JP 57099595A JP 9959582 A JP9959582 A JP 9959582A JP S58216460 A JPS58216460 A JP S58216460A
Authority
JP
Japan
Prior art keywords
light
region
semiconductor
absorbed
semiconductor layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57099595A
Other languages
Japanese (ja)
Inventor
Kazuo Kondo
和夫 近藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP57099595A priority Critical patent/JPS58216460A/en
Publication of JPS58216460A publication Critical patent/JPS58216460A/en
Pending legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/02Structural details or components not essential to laser action
    • H01S5/026Monolithically integrated components, e.g. waveguides, monitoring photo-detectors, drivers
    • H01S5/0262Photo-diodes, e.g. transceiver devices, bidirectional devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/10Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
    • H01S5/12Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region the resonator having a periodic structure, e.g. in distributed feedback [DFB] lasers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/06Arrangements for controlling the laser output parameters, e.g. by operating on the active medium
    • H01S5/062Arrangements for controlling the laser output parameters, e.g. by operating on the active medium by varying the potential of the electrodes
    • H01S5/06233Controlling other output parameters than intensity or frequency
    • H01S5/06243Controlling other output parameters than intensity or frequency controlling the position or direction of the emitted beam

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
  • Led Devices (AREA)
  • Photo Coupler, Interrupter, Optical-To-Optical Conversion Devices (AREA)

Abstract

PURPOSE:To enable to form a logic arithmetic circuit by forming a photoreceiving region and a light emitting region on a high resistance substrate and suitably combining them. CONSTITUTION:A photoreceiving region D1 is composed of semiconductor layers 2, 3, 4, being electrically non-conductive, but when an input light of vertical direction is absorbed to the layer 3, it becomes conductive. A light emitting region S1 is a distributed feedback type laser which has semiconductor regions 7 (3), 6(4), 5(3), a semiconductor layer 2 and diffraction gratings 6(2), 8(2)'. Applied current Jd is increased larger than a threshold current Jth of a laser. Since the forbidden band width of an InGaAsP is decreased smaller than that of tan InP, the layer 3 and the region 5(3) have a carrier enclosing effect. The light which is absorbed at the region 2 and emitted from the region 5(3) passes through the InP without being absorbed. Accordingly, the direction of the input light can be arbitrarily selected except the direction for crossing the region S1 in the plane with elevational directions. The direction of the output light (y) can be arbitrarily selected except the direction for crossing the light receiving regions D1, D2 in the plane.

Description

【発明の詳細な説明】 発明の技術分野 本発明は、同一基板に受光領域と発光領域とが形成され
、それ等を駆動して論理演算を行なう形式の光集積回路
装置に関する。
TECHNICAL FIELD OF THE INVENTION The present invention relates to an optical integrated circuit device in which a light receiving region and a light emitting region are formed on the same substrate and are driven to perform logical operations.

従来技術と問題点 近年、光集積回路は種々のものが提案されているが、論
理演算用として具体的なものは数少ないようである。
BACKGROUND ART AND PROBLEMS In recent years, various types of optical integrated circuits have been proposed, but there seem to be only a few that are specifically designed for logical operations.

発明の目的 本発明は、高抵抗基板に受光領域及び発光領域を形成し
、それ等を適宜組合せることに依り論理演算回路を構成
した光集積回路を提供するものである。
OBJECTS OF THE INVENTION The present invention provides an optical integrated circuit in which a light-receiving region and a light-emitting region are formed on a high-resistance substrate, and a logic operation circuit is constructed by appropriately combining these regions.

発明の実施例 第1図は本発明に依る論理和(OR)演算素子の回路図
である。
Embodiment of the Invention FIG. 1 is a circuit diagram of an OR operation element according to the present invention.

図に於いて、D、 、 D、は受光領域、S、は発光領
域、Jは電源、xl、町は入力光、yは出力光をそれぞ
れ示す。
In the figure, D, , D indicate a light receiving area, S indicates a light emitting area, J indicates a power source, xl, town indicates input light, and y indicates output light, respectively.

この回路に於いて、受光領域り、 、 Dtのいずれか
一方または双方に光が入射されると、それ等受光領域り
、 、 Dtのいずれか一方または双方が導通するので
発光領域SIに電流が流れ光を出力する。
In this circuit, when light is incident on one or both of the light-receiving regions, , and Dt, one or both of the light-receiving regions, , and Dt becomes conductive, so that a current flows in the light-emitting region SI. Outputs flowing light.

次の表1は真理値表である。Table 1 below is a truth table.

表  1 第2図は第1図の回路を具体化した装置の要部平面図で
あり、第3図は第2図の線α−α′(二於ける要部断面
図であって、第1図(=関して説明した部分と同部分は
同記号で指示しである。
Table 1 Figure 2 is a plan view of the main parts of a device embodying the circuit shown in Figure 1, and Figure 3 is a sectional view of the main parts taken along line α-α' (2) in Figure 2. Figure 1 (The same parts as those explained with respect to = are indicated by the same symbols.

図に於いて、1は高抵抗(i) InP基板、2は1型
1nP半導体層、3はInPに格子整合させたi型In
GaAzP半導体層、4はi型JrLP半導体層、5(
3)ハル+型1nGaAzP半導体領域、6(2)はP
+型1nP光回折格子、6(4)はP+型1rLP半導
体領域、7(2)はInP 1mm格子台させたi型1
nGaAsP光回折格子、7(3)はInPに格子整合
させた寥型1nGaAzP半導体領域、8 (2) 、
 8 (4)はt型1nP半導体領域、10は表面保護
膜、20 、21は電極、30は電源をそれぞれ示す。
In the figure, 1 is a high resistance (i) InP substrate, 2 is a 1-type 1nP semiconductor layer, and 3 is an i-type InP substrate lattice-matched to InP.
GaAzP semiconductor layer, 4 is i-type JrLP semiconductor layer, 5 (
3) Hull + type 1nGaAzP semiconductor region, 6(2) is P
+ type 1nP optical diffraction grating, 6(4) is P+ type 1rLP semiconductor region, 7(2) is i type 1 with InP 1mm grating base.
nGaAsP optical diffraction grating, 7(3) is a 1nGaAzP semiconductor region lattice-matched to InP, 8(2),
8 (4) is a t-type 1nP semiconductor region, 10 is a surface protective film, 20 and 21 are electrodes, and 30 is a power source.

次に前記実施例を製造する場合の工程の概略に。Next, an outline of the process for manufacturing the above example will be given.

ついて’W3図と第4図乃至第17図を参照しつつ説明
する。
This will be explained with reference to Figure W3 and Figures 4 to 17.

第4図参照 (1)厚さ約300(μyyt)、比抵抗106〔Ω−
cam)以上のi型1nP基板1を用意する。尚、記号
α、α′は第2図に見られる切断線α−α′で切断され
た面であることを表わしている。
See Figure 4 (1) Thickness approximately 300 (μyyt), specific resistance 106 [Ω-
cam) or above is prepared. Note that the symbols α and α' represent the planes cut along the cutting line α-α' shown in FIG.

第5図参照 (2)液相成長法にて、C型1nP半導体層2を厚さ例
えば2〔μm〕程度、キャリヤ濃度を例えば1 x 1
()+8 (、,7!−3)程度として成長させる。
Refer to FIG. 5 (2) Using the liquid phase growth method, the C-type 1nP semiconductor layer 2 is grown to a thickness of, for example, about 2 [μm] and a carrier concentration of, for example, 1 x 1.
It is grown to about ()+8 (,,7!-3).

第6図参照 (6)通常のフォト・リングラフィ技術(二で、フォト
・レジストのマスク膜31を形成する。
See FIG. 6. (6) Ordinary photo phosphorography technique (Step 2: Form a photoresist mask film 31.

第7図参照 へ (4)マスク膜31にて選択的に保護された半導体層2
のウェット・エツチングを行ない、凹所2A、2Bを形
成する。エツチングの深さはレーデの発振波長に依存す
る。
See FIG. 7 (4) Semiconductor layer 2 selectively protected by mask film 31
Wet etching is performed to form recesses 2A and 2B. The depth of etching depends on the oscillation wavelength of the radar.

第8図参照 (5)  フォト・レジストからなる回折格子用マスク
膜32を形成する。格子パターンの描画には、電子ビー
ム露光技術或いは2光束レーザ干渉法を使用すると良い
。格子のピッチはレーザの発振波長に依って決まる。
Refer to FIG. 8 (5) A diffraction grating mask film 32 made of photoresist is formed. It is preferable to use electron beam exposure technology or two-beam laser interferometry to draw the grating pattern. The pitch of the grating is determined by the oscillation wavelength of the laser.

第9図参照 (6)化学エツチング法にて、再び半導体層2のエツチ
ングを行ない、その深さは、例えば基板1の表面が露出
するまでとする。これに依り、回折格子が形成される。
Refer to FIG. 9 (6) The semiconductor layer 2 is etched again by the chemical etching method, and the etching depth is set, for example, until the surface of the substrate 1 is exposed. This forms a diffraction grating.

第10図参照 (7)  マスク膜32 、31を除去する。See Figure 10 (7) Remove mask films 32 and 31.

(8)液相成長法(:てi型IルGaAzP半導体層3
を成長させる。その厚さは、凹所2A、2Eが埋められ
て表面が平坦になる程度とする。
(8) Liquid phase growth method (i-type I-GaAzP semiconductor layer 3
grow. The thickness is such that the recesses 2A and 2E are filled and the surface becomes flat.

第11図参照 (9)選択エツチング液、例えば弗酸:硝酸(1:1)
を用いて半導体層乙のエツチングを行ない、半導体層2
の表面を露出させる。
See Figure 11 (9) Selective etching solution, e.g. hydrofluoric acid: nitric acid (1:1)
The semiconductor layer 2 is etched using the semiconductor layer 2.
expose the surface of

第12図参照 (10)液相成長法にて1型1nP半導体層4を成長さ
せる。その厚さは約2〔μm〕、キャリヤ濃度は約5 
x 1017 (,77!−3)である。
Refer to FIG. 12 (10) A 1-type 1nP semiconductor layer 4 is grown by a liquid phase growth method. Its thickness is approximately 2 [μm], and the carrier concentration is approximately 5
x 1017 (,77!-3).

第15図参照 (11)フォト・レジストからなる拡散用マスク33を
形成する。
Refer to FIG. 15 (11) A diffusion mask 33 made of photoresist is formed.

(12)気相拡散法にて例えば亜鉛の拡散を行ない、i
型1nGaAsP半導体層3の一部ニp+型1nGaA
zp半導体領域5(3)を、ル1型1nP半導体層4の
一部にp1型1nP半導体領域6(4)をそれぞれ形成
し、また、半導体層2喀二依り形成した回折格子の一部
もp型1nP光回折格子6(2)とする。
(12) Diffusion of, for example, zinc by the gas phase diffusion method, i
Part of the type 1nGaAsP semiconductor layer 3 is p+ type 1nGaA
A zp semiconductor region 5 (3) and a p1 type 1nP semiconductor region 6 (4) are formed in a part of the 1nP semiconductor layer 4, respectively, and a part of the diffraction grating formed in the semiconductor layer 2 is also formed. It is assumed to be a p-type 1nP optical diffraction grating 6 (2).

第14図参照 (13)フォト・レジストからなる拡散用マスク36を
除去する。
Refer to FIG. 14 (13) The diffusion mask 36 made of photoresist is removed.

(14)プロトン照射用マスク34を形成する。これは
例えば蒸着法(=依り金(A u、)膜を形成し、それ
を通常のフォト・リソグラフィ技術にてパタ−ニングす
ること(二依り形成する。
(14) Form a mask 34 for proton irradiation. This can be done, for example, by forming a metal (Au) film using a vapor deposition method, and then patterning it using a normal photolithography technique.

(15)プロトンを照射すること域−依り、半導体層2
.6,4を選択的に高抵抗化し、を型1nGaAzP半
導体領域7(3)、を型1nP半導体領域8 (2) 
、 8(4)を形成する。また、半導体層2で作製した
回折格子の一部も同時に高抵抗化されるので、これを記
号8(2)’で指示しである。
(15) Proton irradiation area - Depending on the semiconductor layer 2
.. 6 and 4 are selectively made high in resistance to form a type 1nGaAzP semiconductor region 7 (3) and a type 1nP semiconductor region 8 (2).
, forming 8(4). Further, since a part of the diffraction grating made of the semiconductor layer 2 is also made to have a high resistance at the same time, this is indicated by the symbol 8(2)'.

第15図参照 (16)プロトン照射用マスク64を除去してから新た
なプロトン照射用マスク55を形成する。
Refer to FIG. 15 (16) After removing the proton irradiation mask 64, a new proton irradiation mask 55 is formed.

(17)プロトン照射を行なって半導体層4の一部を高
抵抗化しi型1nP半導体領域8(4)を形成する。
(17) Perform proton irradiation to increase the resistance of a part of the semiconductor layer 4 to form an i-type 1nP semiconductor region 8 (4).

第16図参照 (18)プロトン照射用マスク65を除去してから、化
学気相堆積法にて窒化シリコン膜を厚さ例えば2000
 (A)程度に形成する。
See FIG. 16. (18) After removing the proton irradiation mask 65, a silicon nitride film is deposited to a thickness of, for example, 2,000 yen by chemical vapor deposition.
Form to about (A).

(19)窒化シリコン膜を通常のフォト・リソグラフィ
技術にてパターニングして保護膜10とする。
(19) The silicon nitride film is patterned using normal photolithography technology to form the protective film 10.

第17図参照 (20)フォト・レジストからなるp側電極マスク膜(
図示せず)を形成してからAu、/Zn(亜鉛)/At
Lの蒸着を行ない、マスク膜を除去することに依り前記
蒸着膜を所謂リフト・オフ法に依ってパターニングし、
これを熱処理して合金化することに依りp側電極21を
形成する。
See Figure 17 (20) P-side electrode mask film made of photoresist (
(not shown) and then Au, /Zn (zinc) /At
By depositing L and removing the mask film, the deposited film is patterned by a so-called lift-off method,
The p-side electrode 21 is formed by heat-treating and alloying this.

第5図参照 (21)フォト・レジストからなるル側電極マスク膜(
図示せず)を形成してからAtb/AtL−Ge (ゲ
ルマニウム)の蒸着を行ない、これを前記同様リフト・
オフ法に依ってパターニングし、合金化することに依り
ル側電極20とする。
See Figure 5. (21) Side electrode mask film made of photoresist (
(not shown), Atb/AtL-Ge (germanium) is vapor-deposited, and then lift and
The side electrode 20 is formed by patterning and alloying using the OFF method.

この後、チップをステムC−装着し、各電極と外部端子
をArb線で接続し、キャップ封止することに依って完
成する。
Thereafter, the chip is mounted on the stem C, each electrode and external terminal are connected with an Arb wire, and the cap is sealed to complete the process.

こノ例では、2層のエピタキシャル成長結晶層を使用し
ているが、第1の層と第2の層との間に例えばル型1r
LGaAsP導波層を設け、そこに回折格子を設けた3
層構造(=するなど種々の改変を考えることができる。
In this example, two epitaxially grown crystal layers are used, and between the first layer and the second layer there is a
3 where an LGaAsP waveguide layer was provided and a diffraction grating was provided there.
Various modifications such as layered structure (=) can be considered.

さて、第1図乃至第6図を参照して一実施例の動作につ
いて説明する。
Now, the operation of one embodiment will be explained with reference to FIGS. 1 to 6.

受光領域DIは半導体層2,3.4で構成され、受光領
域り、−二元が照射されないときは電気的に非導通であ
るが、紙面C二垂直な方向から照射された入力光が半導
体層3で吸収されると受光領域病は導通状態となる。こ
の動作の詳細に関しては特願昭54−171048号(
特開昭56−94786号公報)を参照すると良い。
The light-receiving region DI is composed of semiconductor layers 2, 3.4, and is electrically non-conductive when the - binary is not irradiated. When absorbed by layer 3, the light-receiving area becomes conductive. For details of this operation, please refer to Japanese Patent Application No. 54-171048 (
Please refer to JP-A-56-94786).

発光領域S、は半導体領域7(3) 、6(4) 、 
5(5)及び半導体層2と回折格子6”(2) 、 8
 (2)’を有する分布帰還型レーザである。印加電流
Jdはレーザのしきい値電流Jthより大であることが
必要であるのは云うまでもない。I nGaAzPの禁
止帯幅はInPのそれより小さく設定しであるので、半
導体層6及び半導体領域5(3)はキャリヤの閉じ込め
効果を有している。そして、半導体領域3で吸収され半
導体領域5(6)で発光される光はInP中を吸収され
ることなく通過する。従って、入力光の方向は平面内(
第2図参照)で発光領域S1を横切る方向を除いて任意
に選ぶことができる。また、平面に対する上下方向(第
2図に於いて、紙面幅=垂直)、例えば下方向から基板
1を通して光を入射させることもできる。出力光yの方
向は、平面内で受光領域り、 、 D2を横切る方向を
除いて任意C二選ぶことができる。
The light emitting region S is the semiconductor region 7(3), 6(4),
5 (5) and semiconductor layer 2 and diffraction grating 6'' (2), 8
(2)' It is a distributed feedback laser. It goes without saying that the applied current Jd needs to be larger than the threshold current Jth of the laser. Since the forbidden band width of InGaAzP is set smaller than that of InP, the semiconductor layer 6 and the semiconductor region 5(3) have a carrier confinement effect. The light absorbed by the semiconductor region 3 and emitted by the semiconductor region 5 (6) passes through InP without being absorbed. Therefore, the direction of the input light is in the plane (
(see FIG. 2) can be arbitrarily selected except for the direction across the light emitting region S1. Further, light can also be made to enter through the substrate 1 from above and below the plane (in FIG. 2, paper width = perpendicular), for example from below. The direction of the output light y can be arbitrarily selected except for the direction that crosses the light-receiving area within the plane, D2.

第18図は、第2図に見られる受光領域り、、D。FIG. 18 shows the light receiving area shown in FIG. 2.

を一つの部分にまとめた例を示すものであり、動作的(
:は変りない。
It shows an example of combining the
: remains unchanged.

第19図は、本発明に依る論理積(AND )演算素子
の回路図であり、第1図に関して説明した部分と同部分
を同記号で指示しである。
FIG. 19 is a circuit diagram of an AND operation element according to the present invention, in which the same parts as those explained in connection with FIG. 1 are indicated by the same symbols.

図から判るように、受光領域り、 、 D、 、発光領
域S1は直列C二接続されている。次の表2は、この表
  2 第20図は、第19図の回路を具体化した装置の要部平
面図であり、第21図は第20図の線b−h’に於ける
要部断面図であって、第19図乃至第21図に於いては
第1図乃至第3図に関して説明した部分と同じ部分は同
記号で指示しである。
As can be seen from the figure, the light receiving area, D, and the light emitting area S1 are connected in series. The following Table 2 shows this Table 2. FIG. 20 is a plan view of the main parts of the device embodying the circuit shown in FIG. 19, and FIG. In FIGS. 19 to 21, which are cross-sectional views, the same parts as those explained in connection with FIGS. 1 to 3 are indicated by the same symbols.

本実施例に於ける受光領域D1は半導体層2,3.2で
構成され、受光領域D!は半導体層4.3.2で構成さ
れ、発光領域名は半導体領域7(3)、6(4) 、 
s (3)及び半導体層2及び回折格子6C2)。
The light receiving area D1 in this embodiment is composed of the semiconductor layers 2, 3.2, and the light receiving area D! is composed of semiconductor layers 4.3.2, and the light emitting region names are semiconductor regions 7(3), 6(4),
s (3) and the semiconductor layer 2 and the diffraction grating 6C2).

8 (2)’で構成される。It consists of 8 (2)'.

第22図は本発明に依る3人力の多数決演算素子の回路
図であり、既出の図(=関して説明した部分と同部分を
同記号で指示しである。
FIG. 22 is a circuit diagram of a three-person majority operation element according to the present invention, and the same parts as those explained in the previous figure (= are indicated by the same symbols).

図に於いて、D3 = D4 、DB = DB ? 
D? = ”8 = DO―塙は受光領域、s、 、 
s8. s4は発光領域、xsは入力光をそれぞれ示す
In the figure, D3 = D4, DB = DB?
D? = ”8 = DO-Hanawa is the light receiving area, s, ,
s8. s4 indicates a light emitting region, and xs indicates input light.

この素子では、2個の受光領域例えばり、 、 D。In this device, there are two light-receiving areas, for example, ,D.

を直列接続して1単位の受光回路D4・D、となし、こ
のような受光回路を3単位即ち前記した受光回路D4・
DI+の外に受光回路D6・D丁及び受光回路り。
are connected in series to form one unit of light receiving circuit D4.D, and such light receiving circuits are connected in three units, namely the light receiving circuit D4.
There is a light receiving circuit D6/D6 and a light receiving circuit outside of DI+.

・D、が1個の発光領域S、にそれぞれが直列になるよ
う接続されている。また、三つの光入力x!。
・D is connected to one light emitting region S in series. Also, three optical inputs! .

’t + ”3は、1個の受光領域と1個の受光領域か
らなる光分岐素子D1・S、 、 D、・S、 、 D
3・S、に依ってそれぞれ二つに分岐され、光入力X、
は受光領域D!、 D、 C1光入力x2は受光領域D
7. D、 l:、、光入力x3は受光領域り、 、 
D、にそれぞれ入力されるようになっている。次の表3
は本実施例に於ける真理値表である。
't+''3 is a light branching element D1・S, , D,・S, , D consisting of one light-receiving area and one light-receiving area.
3.S, each is branched into two, and the optical input X,
is the light receiving area D! , D, C1 light input x2 is light receiving area D
7. D, l:,, the light input x3 is the light receiving area, ,
D, respectively. Table 3 below
is a truth table in this embodiment.

表  3 第23図は、第22図の回路を具体化した装置の要部平
面図であり、第24図は第23図の線α−α′に於ける
要部断面図であって、第22図乃至第24図(二於いて
は第1図乃至第3図に関して説明した部分と同じ部分は
同記号で指示しである。
Table 3 FIG. 23 is a plan view of a main part of a device embodying the circuit shown in FIG. 22, and FIG. 22 to 24 (in FIG. 2, the same parts as those described with respect to FIGS. 1 to 3 are indicated by the same symbols.

図に於いて、22乃至27は電極、33は電源をそれぞ
れ示している。尚、電源30 、33はp1型IルGa
AsP半導体領域5(3)とi型1nP半導体層2とで
形成されるpn接合5(5)・2が順方向バイアスとな
るよう接続する。
In the figure, 22 to 27 represent electrodes, and 33 represents a power source. In addition, the power supplies 30 and 33 are p1 type Ile Ga.
The pn junctions 5(5) and 2 formed by the AsP semiconductor region 5(3) and the i-type 1nP semiconductor layer 2 are connected so as to be forward biased.

さて、本実施例(二於ける受光領域D4乃至D9は半導
体層2,5.4で構成され、発光領域sl乃至s4は半
導体領域7 (5) 、 6 (4) 、 5 (3)
及び半導体層2と回折格子6 (2) t s (2)
’で構成される。また、抵抗R百家半導体層3で構成さ
れているが、回路の等価抵抗を他の手段で設定できると
きは不要である。
Now, in this embodiment (2), the light receiving regions D4 to D9 are composed of semiconductor layers 2 and 5.4, and the light emitting regions sl to s4 are composed of semiconductor regions 7 (5), 6 (4), 5 (3).
and semiconductor layer 2 and diffraction grating 6 (2) t s (2)
' Consists of '. Further, although the resistor R is composed of the semiconductor layer 3, it is not necessary when the equivalent resistance of the circuit can be set by other means.

本実施例に於ける光の入力、通過、発光、出方等の関係
は他の実施例と同様であり、また、この技術に依り3人
力以上の多数決演算素子を形成することも容易である。
The relationship of light input, passage, light emission, output, etc. in this embodiment is the same as in other embodiments, and it is also easy to form a majority calculation element powered by three or more people using this technique. .

゛ 前記各実施例では、Ink/InGaAtP系の半導体
を使用したものについて説明したが、他の系、例えば、
GaAs/GaAIAz系についても同様(二実施でき
る。
゛In each of the above embodiments, an example using an Ink/InGaAtP-based semiconductor has been described, but other systems, such as
The same applies to the GaAs/GaAIAz system (two implementations are possible).

発明の効果 本発明に依れば、高抵抗基板に受光領域と発光領域とを
形成し、複数の受光領域と1個の発光領域とが直列或い
は並列に接続されるよう組合せて論理演算回路を構成で
きるので、薇来、実現されていなかった論理演算可能な
光集積回路が提供される。
Effects of the Invention According to the present invention, a light receiving area and a light emitting area are formed on a high resistance substrate, and a logic operation circuit is formed by combining a plurality of light receiving areas and one light emitting area so that they are connected in series or in parallel. Since it can be configured, an optical integrated circuit capable of logical operations, which has not been realized since then, can be provided.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明一実施例の回路図、第2図は第1図の回
路を具体化した装置の要部平面図、第3図は第2図の線
α−α′に於ける要部断面図、第4図乃至第17図は第
3図に見られる装置を製造する工程を説明する為の工程
要所(=於ける半導体装置の要部断面図、第18図は他
の実施例の要部平面図、第19図は他の実施例の回路図
、第20図は第19図の回路を具体化した装置の要部平
面図、第21図は第20図の線h−b’j−於ける要部
断面図、第22図は更C他の実施例の回路図、第23図
は第22図の回路を具体化した装置の要部平面図、第2
4図は第25図C二於ける線α−α′に於ける要部断面
図である。 図に於いて、1は高抵抗(i)InP基板、2はn+梨
型1nP導体屑、3はi型1nGaAsP半導体層、4
はル゛1型1nP半導体層、5(3)はp+梨型1nG
aAsP導体領域、6(2)はP+型1nP光回折格子
、6(4)はp+梨型1nP導体領域、’9(2)’は
t型1rLGaルP光回折格子、7(3)はt型1nG
aAsP半導体領域、8 (2)、8(4)はt型1r
LP半導体領域、10は表面保護膜、20 、21は電
極、30は電源である。 特許出願人 富士通株式会社 代理人 弁理士 玉蟲久五部(外3名)、1 第5図 第7図 第8図 第9図 第10図 第11図 第12図 「 第14図 第+5図 第16図 1 第17図 第18図 a′ 第19図 b          b
FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is a plan view of the main parts of a device embodying the circuit of FIG. 1, and FIG. 4 to 17 are cross-sectional views of main parts of the semiconductor device shown in FIG. 3, and FIG. 19 is a circuit diagram of another embodiment, FIG. 20 is a plan view of a main part of a device embodying the circuit of FIG. 19, and FIG. 21 is a line h-- Fig. 22 is a circuit diagram of another embodiment of C, Fig. 23 is a plan view of the main part of a device embodying the circuit of Fig. 22,
FIG. 4 is a sectional view of a main part taken along line α-α' in FIG. 25C2. In the figure, 1 is a high resistance (i) InP substrate, 2 is an n+ pear-shaped 1nP conductor scrap, 3 is an i-type 1nGaAsP semiconductor layer, 4
1-type 1nP semiconductor layer, 5(3) is p+ pear-type 1nG
aAsP conductor region, 6(2) is P+ type 1nP optical diffraction grating, 6(4) is p+ pear-shaped 1nP conductor region, '9(2)' is t-type 1rLGaP optical diffraction grating, 7(3) is t Type 1nG
aAsP semiconductor region, 8 (2), 8 (4) are t-type 1r
LP semiconductor region, 10 is a surface protection film, 20 and 21 are electrodes, and 30 is a power source. Patent Applicant Fujitsu Limited Agent Patent Attorney Gobe Tamamushi (3 others), 1 Figure 5 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 14 + Figure 5 16 Figure 1 Figure 17 Figure 18 a' Figure 19 b b

Claims (1)

【特許請求の範囲】[Claims] 高抵抗化合物半導体基板と、該基板上に形成され少数キ
ャリヤの活性層への注入で発光する発光領域、前記基板
上に形成され複数個が直列或い1家並列或いは直並列に
接続され且つ前記発光領域に直列接続されて光の照射或
いは非照射で導通或いは非導通となる受光領域を備えて
なることを特徴とする光集積回路装置。
a high-resistance compound semiconductor substrate; a light-emitting region formed on the substrate that emits light by injecting minority carriers into the active layer; a plurality of light-emitting regions formed on the substrate and connected in series, in parallel, or in series and parallel; 1. An optical integrated circuit device comprising a light receiving region connected in series to a light emitting region and becoming conductive or non-conductive when irradiated with light or not.
JP57099595A 1982-06-09 1982-06-09 Light integrated circuit device Pending JPS58216460A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57099595A JPS58216460A (en) 1982-06-09 1982-06-09 Light integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57099595A JPS58216460A (en) 1982-06-09 1982-06-09 Light integrated circuit device

Publications (1)

Publication Number Publication Date
JPS58216460A true JPS58216460A (en) 1983-12-16

Family

ID=14251445

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57099595A Pending JPS58216460A (en) 1982-06-09 1982-06-09 Light integrated circuit device

Country Status (1)

Country Link
JP (1) JPS58216460A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5558566A (en) * 1978-10-25 1980-05-01 Semiconductor Res Found Semiconductor integrated circuit and semiconductor device
JPS55154794A (en) * 1979-05-21 1980-12-02 Ibm Integrated circuit
JPS58147083A (en) * 1982-02-24 1983-09-01 Mitsubishi Electric Corp Semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5558566A (en) * 1978-10-25 1980-05-01 Semiconductor Res Found Semiconductor integrated circuit and semiconductor device
JPS55154794A (en) * 1979-05-21 1980-12-02 Ibm Integrated circuit
JPS58147083A (en) * 1982-02-24 1983-09-01 Mitsubishi Electric Corp Semiconductor device

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