JPS58216460A - Light integrated circuit device - Google Patents

Abstract

PURPOSE:To enable to form a logic arithmetic circuit by forming a photoreceiving region and a light emitting region on a high resistance substrate and suitably combining them. CONSTITUTION:A photoreceiving region D1 is composed of semiconductor layers 2, 3, 4, being electrically non-conductive, but when an input light of vertical direction is absorbed to the layer 3, it becomes conductive. A light emitting region S1 is a distributed feedback type laser which has semiconductor regions 7 (3), 6(4), 5(3), a semiconductor layer 2 and diffraction gratings 6(2), 8(2)'. Applied current Jd is increased larger than a threshold current Jth of a laser. Since the forbidden band width of an InGaAsP is decreased smaller than that of tan InP, the layer 3 and the region 5(3) have a carrier enclosing effect. The light which is absorbed at the region 2 and emitted from the region 5(3) passes through the InP without being absorbed. Accordingly, the direction of the input light can be arbitrarily selected except the direction for crossing the region S1 in the plane with elevational directions. The direction of the output light (y) can be arbitrarily selected except the direction for crossing the light receiving regions D1, D2 in the plane.

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to an optical integrated circuit device in which a light receiving region and a light emitting region are formed on the same substrate and are driven to perform logical operations.

BACKGROUND ART AND PROBLEMS In recent years, various types of optical integrated circuits have been proposed, but there seem to be only a few that are specifically designed for logical operations.

OBJECTS OF THE INVENTION The present invention provides an optical integrated circuit in which a light-receiving region and a light-emitting region are formed on a high-resistance substrate, and a logic operation circuit is constructed by appropriately combining these regions.

Embodiment of the Invention FIG. 1 is a circuit diagram of an OR operation element according to the present invention.

In the figure, D, , D indicate a light receiving area, S indicates a light emitting area, J indicates a power source, xl, town indicates input light, and y indicates output light, respectively.

In this circuit, when light is incident on one or both of the light-receiving regions, , and Dt, one or both of the light-receiving regions, , and Dt becomes conductive, so that a current flows in the light-emitting region SI. Outputs flowing light.

Table 1 below is a truth table.

Table 1 Figure 2 is a plan view of the main parts of a device embodying the circuit shown in Figure 1, and Figure 3 is a sectional view of the main parts taken along line α-α' (2) in Figure 2. Figure 1 (The same parts as those explained with respect to = are indicated by the same symbols.

In the figure, 1 is a high resistance (i) InP substrate, 2 is a 1-type 1nP semiconductor layer, and 3 is an i-type InP substrate lattice-matched to InP.
GaAzP semiconductor layer, 4 is i-type JrLP semiconductor layer, 5 (
3) Hull + type 1nGaAzP semiconductor region, 6(2) is P
+ type 1nP optical diffraction grating, 6(4) is P+ type 1rLP semiconductor region, 7(2) is i type 1 with InP 1mm grating base.
nGaAsP optical diffraction grating, 7(3) is a 1nGaAzP semiconductor region lattice-matched to InP, 8(2),
8 (4) is a t-type 1nP semiconductor region, 10 is a surface protective film, 20 and 21 are electrodes, and 30 is a power source.

Next, an outline of the process for manufacturing the above example will be given.

This will be explained with reference to Figure W3 and Figures 4 to 17.

See Figure 4 (1) Thickness approximately 300 (μyyt), specific resistance 106 [Ω-
cam) or above is prepared. Note that the symbols α and α' represent the planes cut along the cutting line α-α' shown in FIG.

Refer to FIG. 5 (2) Using the liquid phase growth method, the C-type 1nP semiconductor layer 2 is grown to a thickness of, for example, about 2 [μm] and a carrier concentration of, for example, 1 x 1.
It is grown to about ()+8 (,,7!-3).

See FIG. 6. (6) Ordinary photo phosphorography technique (Step 2: Form a photoresist mask film 31.

See FIG. 7 (4) Semiconductor layer 2 selectively protected by mask film 31
Wet etching is performed to form recesses 2A and 2B. The depth of etching depends on the oscillation wavelength of the radar.

Refer to FIG. 8 (5) A diffraction grating mask film 32 made of photoresist is formed. It is preferable to use electron beam exposure technology or two-beam laser interferometry to draw the grating pattern. The pitch of the grating is determined by the oscillation wavelength of the laser.

Refer to FIG. 9 (6) The semiconductor layer 2 is etched again by the chemical etching method, and the etching depth is set, for example, until the surface of the substrate 1 is exposed. This forms a diffraction grating.

See Figure 10 (7) Remove mask films 32 and 31.

(8) Liquid phase growth method (i-type I-GaAzP semiconductor layer 3
grow. The thickness is such that the recesses 2A and 2E are filled and the surface becomes flat.

See Figure 11 (9) Selective etching solution, e.g. hydrofluoric acid: nitric acid (1:1)
The semiconductor layer 2 is etched using the semiconductor layer 2.
expose the surface of

Refer to FIG. 12 (10) A 1-type 1nP semiconductor layer 4 is grown by a liquid phase growth method. Its thickness is approximately 2 [μm], and the carrier concentration is approximately 5
x 1017 (,77!-3).

Refer to FIG. 15 (11) A diffusion mask 33 made of photoresist is formed.

(12) Diffusion of, for example, zinc by the gas phase diffusion method, i
Part of the type 1nGaAsP semiconductor layer 3 is p+ type 1nGaA
A zp semiconductor region 5 (3) and a p1 type 1nP semiconductor region 6 (4) are formed in a part of the 1nP semiconductor layer 4, respectively, and a part of the diffraction grating formed in the semiconductor layer 2 is also formed. It is assumed to be a p-type 1nP optical diffraction grating 6 (2).

Refer to FIG. 14 (13) The diffusion mask 36 made of photoresist is removed.

(14) Form a mask 34 for proton irradiation. This can be done, for example, by forming a metal (Au) film using a vapor deposition method, and then patterning it using a normal photolithography technique.

(15) Proton irradiation area - Depending on the semiconductor layer 2
．． 6 and 4 are selectively made high in resistance to form a type 1nGaAzP semiconductor region 7 (3) and a type 1nP semiconductor region 8 (2).
, forming 8(4). Further, since a part of the diffraction grating made of the semiconductor layer 2 is also made to have a high resistance at the same time, this is indicated by the symbol 8(2)'.

Refer to FIG. 15 (16) After removing the proton irradiation mask 64, a new proton irradiation mask 55 is formed.

(17) Perform proton irradiation to increase the resistance of a part of the semiconductor layer 4 to form an i-type 1nP semiconductor region 8 (4).

See FIG. 16. (18) After removing the proton irradiation mask 65, a silicon nitride film is deposited to a thickness of, for example, 2,000 yen by chemical vapor deposition.
Form to about (A).

(19) The silicon nitride film is patterned using normal photolithography technology to form the protective film 10.

See Figure 17 (20) P-side electrode mask film made of photoresist (
(not shown) and then Au, /Zn (zinc) /At
By depositing L and removing the mask film, the deposited film is patterned by a so-called lift-off method,
The p-side electrode 21 is formed by heat-treating and alloying this.

See Figure 5. (21) Side electrode mask film made of photoresist (
(not shown), Atb/AtL-Ge (germanium) is vapor-deposited, and then lift and
The side electrode 20 is formed by patterning and alloying using the OFF method.

Thereafter, the chip is mounted on the stem C, each electrode and external terminal are connected with an Arb wire, and the cap is sealed to complete the process.

In this example, two epitaxially grown crystal layers are used, and between the first layer and the second layer there is a
3 where an LGaAsP waveguide layer was provided and a diffraction grating was provided there.
Various modifications such as layered structure (=) can be considered.

Now, the operation of one embodiment will be explained with reference to FIGS. 1 to 6.

The light-receiving region DI is composed of semiconductor layers 2, 3.4, and is electrically non-conductive when the - binary is not irradiated. When absorbed by layer 3, the light-receiving area becomes conductive. For details of this operation, please refer to Japanese Patent Application No. 54-171048 (
Please refer to JP-A-56-94786).

The light emitting region S is the semiconductor region 7(3), 6(4),
5 (5) and semiconductor layer 2 and diffraction grating 6'' (2), 8
(2)' It is a distributed feedback laser. It goes without saying that the applied current Jd needs to be larger than the threshold current Jth of the laser. Since the forbidden band width of InGaAzP is set smaller than that of InP, the semiconductor layer 6 and the semiconductor region 5(3) have a carrier confinement effect. The light absorbed by the semiconductor region 3 and emitted by the semiconductor region 5 (6) passes through InP without being absorbed. Therefore, the direction of the input light is in the plane (
(see FIG. 2) can be arbitrarily selected except for the direction across the light emitting region S1. Further, light can also be made to enter through the substrate 1 from above and below the plane (in FIG. 2, paper width = perpendicular), for example from below. The direction of the output light y can be arbitrarily selected except for the direction that crosses the light-receiving area within the plane, D2.

FIG. 18 shows the light receiving area shown in FIG. 2.

It shows an example of combining the
: remains unchanged.

FIG. 19 is a circuit diagram of an AND operation element according to the present invention, in which the same parts as those explained in connection with FIG. 1 are indicated by the same symbols.

As can be seen from the figure, the light receiving area, D, and the light emitting area S1 are connected in series. The following Table 2 shows this Table 2. FIG. 20 is a plan view of the main parts of the device embodying the circuit shown in FIG. 19, and FIG. In FIGS. 19 to 21, which are cross-sectional views, the same parts as those explained in connection with FIGS. 1 to 3 are indicated by the same symbols.

The light receiving area D1 in this embodiment is composed of the semiconductor layers 2, 3.2, and the light receiving area D! is composed of semiconductor layers 4.3.2, and the light emitting region names are semiconductor regions 7(3), 6(4),
s (3) and the semiconductor layer 2 and the diffraction grating 6C2).

It consists of 8 (2)'.

FIG. 22 is a circuit diagram of a three-person majority operation element according to the present invention, and the same parts as those explained in the previous figure (= are indicated by the same symbols).

In the figure, D3 = D4, DB = DB?
D? = ”8 = DO-Hanawa is the light receiving area, s, ,
s8. s4 indicates a light emitting region, and xs indicates input light.

In this device, there are two light-receiving areas, for example, ,D.

are connected in series to form one unit of light receiving circuit D4.D, and such light receiving circuits are connected in three units, namely the light receiving circuit D4.
There is a light receiving circuit D6/D6 and a light receiving circuit outside of DI+.

・D is connected to one light emitting region S in series. Also, three optical inputs! .

't+''3 is a light branching element D1・S, , D,・S, , D consisting of one light-receiving area and one light-receiving area.
3.S, each is branched into two, and the optical input X,
is the light receiving area D! , D, C1 light input x2 is light receiving area D
7. D, l:,, the light input x3 is the light receiving area, ,
D, respectively. Table 3 below
is a truth table in this embodiment.

Table 3 FIG. 23 is a plan view of a main part of a device embodying the circuit shown in FIG. 22, and FIG. 22 to 24 (in FIG. 2, the same parts as those described with respect to FIGS. 1 to 3 are indicated by the same symbols.

In the figure, 22 to 27 represent electrodes, and 33 represents a power source. In addition, the power supplies 30 and 33 are p1 type Ile Ga.
The pn junctions 5(5) and 2 formed by the AsP semiconductor region 5(3) and the i-type 1nP semiconductor layer 2 are connected so as to be forward biased.

Now, in this embodiment (2), the light receiving regions D4 to D9 are composed of semiconductor layers 2 and 5.4, and the light emitting regions sl to s4 are composed of semiconductor regions 7 (5), 6 (4), 5 (3).
and semiconductor layer 2 and diffraction grating 6 (2) t s (2)
' Consists of '. Further, although the resistor R is composed of the semiconductor layer 3, it is not necessary when the equivalent resistance of the circuit can be set by other means.

The relationship of light input, passage, light emission, output, etc. in this embodiment is the same as in other embodiments, and it is also easy to form a majority calculation element powered by three or more people using this technique. .

゛In each of the above embodiments, an example using an Ink/InGaAtP-based semiconductor has been described, but other systems, such as
The same applies to the GaAs/GaAIAz system (two implementations are possible).

Effects of the Invention According to the present invention, a light receiving area and a light emitting area are formed on a high resistance substrate, and a logic operation circuit is formed by combining a plurality of light receiving areas and one light emitting area so that they are connected in series or in parallel. Since it can be configured, an optical integrated circuit capable of logical operations, which has not been realized since then, can be provided.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is a plan view of the main parts of a device embodying the circuit of FIG. 1, and FIG. 4 to 17 are cross-sectional views of main parts of the semiconductor device shown in FIG. 3, and FIG. 19 is a circuit diagram of another embodiment, FIG. 20 is a plan view of a main part of a device embodying the circuit of FIG. 19, and FIG. 21 is a line h-- Fig. 22 is a circuit diagram of another embodiment of C, Fig. 23 is a plan view of the main part of a device embodying the circuit of Fig. 22,
FIG. 4 is a sectional view of a main part taken along line α-α' in FIG. 25C2. In the figure, 1 is a high resistance (i) InP substrate, 2 is an n+ pear-shaped 1nP conductor scrap, 3 is an i-type 1nGaAsP semiconductor layer, 4
1-type 1nP semiconductor layer, 5(3) is p+ pear-type 1nG
aAsP conductor region, 6(2) is P+ type 1nP optical diffraction grating, 6(4) is p+ pear-shaped 1nP conductor region, '9(2)' is t-type 1rLGaP optical diffraction grating, 7(3) is t Type 1nG
aAsP semiconductor region, 8 (2), 8 (4) are t-type 1r
LP semiconductor region, 10 is a surface protection film, 20 and 21 are electrodes, and 30 is a power source. Patent Applicant Fujitsu Limited Agent Patent Attorney Gobe Tamamushi (3 others), 1 Figure 5 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 14 + Figure 5 16 Figure 1 Figure 17 Figure 18 a' Figure 19 b b

Claims (1)

[Claims] a high-resistance compound semiconductor substrate; a light-emitting region formed on the substrate that emits light by injecting minority carriers into the active layer; a plurality of light-emitting regions formed on the substrate and connected in series, in parallel, or in series and parallel; 1. An optical integrated circuit device comprising a light receiving region connected in series to a light emitting region and becoming conductive or non-conductive when irradiated with light or not.