JPS5558545A - Manufacture of eielectric insulation separation base plate - Google Patents

Manufacture of eielectric insulation separation base plate

Info

Publication number
JPS5558545A
JPS5558545A JP13149278A JP13149278A JPS5558545A JP S5558545 A JPS5558545 A JP S5558545A JP 13149278 A JP13149278 A JP 13149278A JP 13149278 A JP13149278 A JP 13149278A JP S5558545 A JPS5558545 A JP S5558545A
Authority
JP
Japan
Prior art keywords
wafer
film
regions
single crystal
eielectric
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13149278A
Other languages
Japanese (ja)
Inventor
Shigeru Kawamata
Kiyoshi Tsukuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP13149278A priority Critical patent/JPS5558545A/en
Publication of JPS5558545A publication Critical patent/JPS5558545A/en
Pending legal-status Critical Current

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  • Element Separation (AREA)

Abstract

PURPOSE: To prevent bending at the time of scribing, by forming a plurality of island regions on a semiconductor wafer and reinforcing the scribe region with polycrystalline semiconductor including single crystal at the time when the wafer including the plurality of island regions is scribed.
CONSTITUTION: SiO2 film is coated on single crystal Si wafer 21. By selectively removing this and operating photoetching, separation grooves 22 are formed. Then, the entire surface is covered with SiO2 film 23. Next, film 23 of regions 26, which are to be scribed, is removed, and polycrystalline Si layer 24, of sufficient thicknes to withstand handling, is grown on the entire surface. By this, mesh-shaped single crystal Si layer 27 is grown on the surface where film 23 has been removed and wafer 21 is exposed. As a result, the strength of wafer 21 is increased. Subsequently, wafer 21 is ground, and thereby a plurality of island regions 21a, 21b, surrounded by separation grooves 22, are exposed. Scribing is done on regions 26. By this, wafer 21 is prevented from bending.
COPYRIGHT: (C)1980,JPO&Japio
JP13149278A 1978-10-27 1978-10-27 Manufacture of eielectric insulation separation base plate Pending JPS5558545A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13149278A JPS5558545A (en) 1978-10-27 1978-10-27 Manufacture of eielectric insulation separation base plate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13149278A JPS5558545A (en) 1978-10-27 1978-10-27 Manufacture of eielectric insulation separation base plate

Publications (1)

Publication Number Publication Date
JPS5558545A true JPS5558545A (en) 1980-05-01

Family

ID=15059252

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13149278A Pending JPS5558545A (en) 1978-10-27 1978-10-27 Manufacture of eielectric insulation separation base plate

Country Status (1)

Country Link
JP (1) JPS5558545A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50120781A (en) * 1974-03-08 1975-09-22

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50120781A (en) * 1974-03-08 1975-09-22

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