JPS54140487A - Wiring forming method - Google Patents

Wiring forming method

Info

Publication number
JPS54140487A
JPS54140487A JP4777078A JP4777078A JPS54140487A JP S54140487 A JPS54140487 A JP S54140487A JP 4777078 A JP4777078 A JP 4777078A JP 4777078 A JP4777078 A JP 4777078A JP S54140487 A JPS54140487 A JP S54140487A
Authority
JP
Japan
Prior art keywords
film
sio
layer
wiring
impurity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4777078A
Other languages
Japanese (ja)
Inventor
Tatsumi Shirasu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP4777078A priority Critical patent/JPS54140487A/en
Publication of JPS54140487A publication Critical patent/JPS54140487A/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Weting (AREA)
  • Non-Volatile Memory (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

PURPOSE: To eliminate the capacity junction at the overlap area of the wiring layers by distrubuting two wiring layers in flat with no overlap to each other and with the minimum space secured between.
CONSTITUTION: SiO2 film 12, poly-crystal Si film 14 containing the impurity, SiO2 film 16 and Si3N4 film 18 are coated in lamination on Si substrate 10, and then the selective etching is given to make remain film 18a and 16a corresponding to the wiring pattern. Then film 14 is oxidized with use of film 18a and 16a used as the mask to grow thick SiO2 film 20 connecting to SiO2 film 12a, 12b, 16a and 16b each. After this, only film 20 is removed through etching, and film 18a and 18b are protruded there in the eaves form to grow thin SiO2 film 20a. The poly-crystal Si layer containing the impurity is staked on the entire surface, and the anode oxidation is given to split layers 22a W 22c except for layer 22d and 22e on the eaves part to change the surface into SiO2 films 24a W 24c. After this, film 18a and 18b are removed to obtain the wiring in which 14a and 14b of the 1st layer and 22a W 22c of the 2nd layer are aligned alternately.
COPYRIGHT: (C)1979,JPO&Japio
JP4777078A 1978-04-24 1978-04-24 Wiring forming method Pending JPS54140487A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4777078A JPS54140487A (en) 1978-04-24 1978-04-24 Wiring forming method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4777078A JPS54140487A (en) 1978-04-24 1978-04-24 Wiring forming method

Publications (1)

Publication Number Publication Date
JPS54140487A true JPS54140487A (en) 1979-10-31

Family

ID=12784604

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4777078A Pending JPS54140487A (en) 1978-04-24 1978-04-24 Wiring forming method

Country Status (1)

Country Link
JP (1) JPS54140487A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07211690A (en) * 1994-01-12 1995-08-11 Lg Semicon Co Ltd Selective etching method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07211690A (en) * 1994-01-12 1995-08-11 Lg Semicon Co Ltd Selective etching method

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