JPS55111157A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPS55111157A
JPS55111157A JP1820779A JP1820779A JPS55111157A JP S55111157 A JPS55111157 A JP S55111157A JP 1820779 A JP1820779 A JP 1820779A JP 1820779 A JP1820779 A JP 1820779A JP S55111157 A JPS55111157 A JP S55111157A
Authority
JP
Japan
Prior art keywords
layers
type
vertical transistors
layer
base
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1820779A
Other languages
Japanese (ja)
Inventor
Masaru Okumura
Hiroshi Kamijo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP1820779A priority Critical patent/JPS55111157A/en
Publication of JPS55111157A publication Critical patent/JPS55111157A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/0948Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET using CMOS or complementary insulated gate field-effect transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0214Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
    • H01L27/0229Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of bipolar structures
    • H01L27/0233Integrated injection logic structures [I2L]

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Bipolar Transistors (AREA)
  • Bipolar Integrated Circuits (AREA)

Abstract

PURPOSE:To reduce an ineffective base current and effectively increase the current amplification factor of vertical transistors of an I<2>L device, by providing a prescribed layer of high impurity concentration, only under the collector region of the vertical transistors. CONSTITUTION:An n-type embedded layer 32 and an n-type epitaxial layer 33 are provided on a p-type Si substrate 31. Windows are opened, only under portions to be the collector regions of vertical transistors. n<+>-Type embedded layers 34 of higher impurity concentration than the n-type layer 33 are produced by diffusion. An epitaxial layer 35 is produced on the embedded layers 34. At that time, the layers 35, 33 so that layers penetrating emitter-base junctions are provided. An emitter region 36 and a collector region 37 are then produced. Since the high-concentration n<+>-type layers 34 are present only on base-emitter junction portions facing the collector regions 38 of the vertical transistors of an I<2>L device, base currents flow through the layers 34. This results in reducing an ineffective current and increasing the current amplification factor.
JP1820779A 1979-02-19 1979-02-19 Semiconductor integrated circuit device Pending JPS55111157A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1820779A JPS55111157A (en) 1979-02-19 1979-02-19 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1820779A JPS55111157A (en) 1979-02-19 1979-02-19 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPS55111157A true JPS55111157A (en) 1980-08-27

Family

ID=11965193

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1820779A Pending JPS55111157A (en) 1979-02-19 1979-02-19 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS55111157A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS517885A (en) * 1974-07-09 1976-01-22 Tokyo Shibaura Electric Co
JPS5150585A (en) * 1974-10-30 1976-05-04 Tokyo Shibaura Electric Co
JPS5183479A (en) * 1975-01-20 1976-07-22 Tokyo Shibaura Electric Co

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS517885A (en) * 1974-07-09 1976-01-22 Tokyo Shibaura Electric Co
JPS5150585A (en) * 1974-10-30 1976-05-04 Tokyo Shibaura Electric Co
JPS5183479A (en) * 1975-01-20 1976-07-22 Tokyo Shibaura Electric Co

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