JPS5492079A - Dynamic mos transistor memory - Google Patents
Dynamic mos transistor memoryInfo
- Publication number
- JPS5492079A JPS5492079A JP16087177A JP16087177A JPS5492079A JP S5492079 A JPS5492079 A JP S5492079A JP 16087177 A JP16087177 A JP 16087177A JP 16087177 A JP16087177 A JP 16087177A JP S5492079 A JPS5492079 A JP S5492079A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- substrate
- junction
- memory capacity
- capacity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/33—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor extending under the transistor
Landscapes
- Semiconductor Memories (AREA)
Abstract
PURPOSE:To secure a large amount of the memory capacity with a small cell area by making use of the junction between the substrate and the buried layer provided to the substrate. CONSTITUTION:N<+>-buried layer 11 is provided to P-type substrate 10a, and P- epitaxial layer 10b is laminated. After the partial oxidation at the field part, N<+>- layer 13 is provided to reach layer 11 from the surface, and then poly Si15 is formed on oxidized surface 14. N-type source-drain 12 is formed through self-matching and via mask 15. Then SiO2 is laminated with the electrode window provided to layer 12 of one side, thus forming wiring 16. Wiring 16 becomes the bit signal line, and layer 11 is turned to the information memory capacity via the Pn-junction formed by the substrate. In such constitution, the memory capacity can be designed into a large scale in a simple way, and the varying amount can be increased for the floating capacity of the bit line. As a result, the assured writing and reading action is ensured. The pn-junction capacity is secured in the form of the buried layer, thus decreasing the occupied area.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16087177A JPS5492079A (en) | 1977-12-28 | 1977-12-28 | Dynamic mos transistor memory |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16087177A JPS5492079A (en) | 1977-12-28 | 1977-12-28 | Dynamic mos transistor memory |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5492079A true JPS5492079A (en) | 1979-07-20 |
Family
ID=15724162
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16087177A Pending JPS5492079A (en) | 1977-12-28 | 1977-12-28 | Dynamic mos transistor memory |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5492079A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01292851A (en) * | 1988-05-20 | 1989-11-27 | Nec Corp | Semiconductor memory device |
-
1977
- 1977-12-28 JP JP16087177A patent/JPS5492079A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01292851A (en) * | 1988-05-20 | 1989-11-27 | Nec Corp | Semiconductor memory device |
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