JPS54146549A - Information processor - Google Patents

Information processor

Info

Publication number
JPS54146549A
JPS54146549A JP5472778A JP5472778A JPS54146549A JP S54146549 A JPS54146549 A JP S54146549A JP 5472778 A JP5472778 A JP 5472778A JP 5472778 A JP5472778 A JP 5472778A JP S54146549 A JPS54146549 A JP S54146549A
Authority
JP
Japan
Prior art keywords
control part
request
buffer
storage
execution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5472778A
Other languages
English (en)
Other versions
JPS5710461B2 (ja
Inventor
Naoki Yamada
Kenichi Wada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP5472778A priority Critical patent/JPS54146549A/ja
Priority to US06/033,449 priority patent/US4318172A/en
Priority to GB7914559A priority patent/GB2029612B/en
Priority to DE2918357A priority patent/DE2918357C2/de
Publication of JPS54146549A publication Critical patent/JPS54146549A/ja
Publication of JPS5710461B2 publication Critical patent/JPS5710461B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G06F11/1405—Saving, restoring, recovering or retrying at machine instruction level
    • G06F11/141—Saving, restoring, recovering or retrying at machine instruction level for bus or memory accesses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3834—Maintaining memory consistency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
  • Retry When Errors Occur (AREA)
JP5472778A 1978-05-09 1978-05-09 Information processor Granted JPS54146549A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP5472778A JPS54146549A (en) 1978-05-09 1978-05-09 Information processor
US06/033,449 US4318172A (en) 1978-05-09 1979-04-26 Store data buffer control system
GB7914559A GB2029612B (en) 1978-05-09 1979-04-26 Data buffer control system
DE2918357A DE2918357C2 (de) 1978-05-09 1979-05-07 Speicherdaten-Puffer-Steuereinrichtung

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5472778A JPS54146549A (en) 1978-05-09 1978-05-09 Information processor

Publications (2)

Publication Number Publication Date
JPS54146549A true JPS54146549A (en) 1979-11-15
JPS5710461B2 JPS5710461B2 (ja) 1982-02-26

Family

ID=12978827

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5472778A Granted JPS54146549A (en) 1978-05-09 1978-05-09 Information processor

Country Status (4)

Country Link
US (1) US4318172A (ja)
JP (1) JPS54146549A (ja)
DE (1) DE2918357C2 (ja)
GB (1) GB2029612B (ja)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2121997B (en) * 1982-06-11 1985-10-09 Int Computers Ltd Testing modular data processing systems
JPS59119450A (ja) * 1982-12-25 1984-07-10 Fujitsu Ltd マシン・チエツク処理方式
JPS60142418A (ja) * 1983-12-28 1985-07-27 Hitachi Ltd 入出力エラ−回復方式
US4682284A (en) * 1984-12-06 1987-07-21 American Telephone & Telegraph Co., At&T Bell Lab. Queue administration method and apparatus
JPH0668739B2 (ja) * 1985-01-28 1994-08-31 株式会社日立製作所 データ処理装置
JPH0789328B2 (ja) * 1988-05-31 1995-09-27 日本電気株式会社 データ処理装置
JPH0752399B2 (ja) * 1988-06-30 1995-06-05 インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン 記憶システム
KR930001056B1 (ko) * 1988-11-10 1993-02-13 미쯔비시덴끼 가부시끼가이샤 하드웨어 소터유니트 및 그의 에러수집방법
JPH087715B2 (ja) * 1990-11-15 1996-01-29 インターナショナル・ビジネス・マシーンズ・コーポレイション データ処理装置及びアクセス制御方法
JPH0830506A (ja) * 1994-07-20 1996-02-02 Fujitsu Ltd データ転送制御方法およびデータ転送回路
US6665792B1 (en) * 1996-11-13 2003-12-16 Intel Corporation Interface to a memory system for a processor having a replay system
JP5465995B2 (ja) * 2009-01-06 2014-04-09 株式会社日立国際電気 基板処理システム、収集ユニット、基板処理装置のデータ処理方法および基板処理装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1124017A (en) * 1964-12-17 1968-08-14 English Electric Computers Ltd Data storage apparatus
US3533082A (en) * 1968-01-15 1970-10-06 Ibm Instruction retry apparatus including means for restoring the original contents of altered source operands
US3564506A (en) * 1968-01-17 1971-02-16 Ibm Instruction retry byte counter
US3764986A (en) * 1972-08-09 1973-10-09 Mi2 Columbus Magnetic tape data processing system
US4034347A (en) * 1975-08-08 1977-07-05 Bell Telephone Laboratories, Incorporated Method and apparatus for controlling a multiprocessor system
US4112562A (en) * 1977-08-10 1978-09-12 Rca Corporation Process of fabricating a cathode ray tube

Also Published As

Publication number Publication date
JPS5710461B2 (ja) 1982-02-26
GB2029612B (en) 1982-08-25
GB2029612A (en) 1980-03-19
DE2918357C2 (de) 1983-01-13
US4318172A (en) 1982-03-02
DE2918357A1 (de) 1979-11-15

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