JPS54145483A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS54145483A
JPS54145483A JP5370078A JP5370078A JPS54145483A JP S54145483 A JPS54145483 A JP S54145483A JP 5370078 A JP5370078 A JP 5370078A JP 5370078 A JP5370078 A JP 5370078A JP S54145483 A JPS54145483 A JP S54145483A
Authority
JP
Japan
Prior art keywords
electrode
fet
source electrode
gaas
ultra
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5370078A
Other languages
Japanese (ja)
Inventor
Hideaki Kozu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP5370078A priority Critical patent/JPS54145483A/en
Publication of JPS54145483A publication Critical patent/JPS54145483A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge

Landscapes

  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE: To obtain an ultra-high frequency GaAs FET by composing the device of a FET with drain and gate electrode metal layers thicker than a source electrode metal layer and a capacitor whose one surface is connected to only this source electrode while the other is grounded.
CONSTITUTION: On semi-insulating GaAs substrate 1, N-type GaAs layer 2 is formed by epitaxial growth, on which thick source electrode 3 is also formed. Next, thin gate electrode 4 is provided into it and thin drain electrode 5 is formed inside of it as well as electrode 4. Then, the reverse surface of chip capacitor 7 is fixed via metallic foil 6 to external electrode 3 protruding more than electrodes 4 and 5 inside of it, and metal wire 8 of a gold tape is led out from the surface and connected to earth coductor 9. At the same time, the reverse surface of substrate 1 is also fixed to earth conductor 9. Consequently, a GaAs FET can be obtained which operates at an ultra-high frequency of more than 4GHz.
COPYRIGHT: (C)1979,JPO&Japio
JP5370078A 1978-05-08 1978-05-08 Semiconductor device Pending JPS54145483A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5370078A JPS54145483A (en) 1978-05-08 1978-05-08 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5370078A JPS54145483A (en) 1978-05-08 1978-05-08 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS54145483A true JPS54145483A (en) 1979-11-13

Family

ID=12950087

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5370078A Pending JPS54145483A (en) 1978-05-08 1978-05-08 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS54145483A (en)

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