JPS5460866A - Electric field effect transistor - Google Patents

Electric field effect transistor

Info

Publication number
JPS5460866A
JPS5460866A JP12788577A JP12788577A JPS5460866A JP S5460866 A JPS5460866 A JP S5460866A JP 12788577 A JP12788577 A JP 12788577A JP 12788577 A JP12788577 A JP 12788577A JP S5460866 A JPS5460866 A JP S5460866A
Authority
JP
Japan
Prior art keywords
electrode
layer
substrate
diode
schottky
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12788577A
Other languages
Japanese (ja)
Inventor
Masaaki Nakatani
Yasuro Mitsui
Shigeru Mitsui
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP12788577A priority Critical patent/JPS5460866A/en
Publication of JPS5460866A publication Critical patent/JPS5460866A/en
Pending legal-status Critical Current

Links

Landscapes

  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE: To improve the matching with the external circuit impedance by installing the diode electrode forming the diode approximate to the gate electrode on the same surface as the semiconductor layer forming FET and then combining these electrodes with the lead wire to form an input impedance matching circuit.
CONSTITUTION: N-type active layer 2 is epitaxial-grown on the region at one side of semi-insulating substrate 1, and source electrode 3 and drain electrode 4 of Au, Ge and Ni are formed there. Then layer 2 is given the mesa etching to expose substrate 1. Al Schottky gate electrode 5 is formed between electrode 3 and 4, and the edge part of 5 is extended onto substrate 1 to form the FET part I. At the same time, N-type layer 2 is epitaxial-grown on the other side of substrate 1 as well with Al Schottky electrode 16 attached. Surrounding electrode 16, Au-Ge-Ni earth electrode 15 is formed with layer 2 mesa-etched to form planar-type Schottky diode part II. After this, electrode 5 and 16 are connected via lead wire 9 to form a matching circuit
COPYRIGHT: (C)1979,JPO&Japio
JP12788577A 1977-10-24 1977-10-24 Electric field effect transistor Pending JPS5460866A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12788577A JPS5460866A (en) 1977-10-24 1977-10-24 Electric field effect transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12788577A JPS5460866A (en) 1977-10-24 1977-10-24 Electric field effect transistor

Publications (1)

Publication Number Publication Date
JPS5460866A true JPS5460866A (en) 1979-05-16

Family

ID=14971050

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12788577A Pending JPS5460866A (en) 1977-10-24 1977-10-24 Electric field effect transistor

Country Status (1)

Country Link
JP (1) JPS5460866A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56140667A (en) * 1980-04-04 1981-11-04 Nec Corp Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56140667A (en) * 1980-04-04 1981-11-04 Nec Corp Semiconductor device

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