JPS5412568A - Aligning method of semiconductor wafers - Google Patents

Aligning method of semiconductor wafers

Info

Publication number
JPS5412568A
JPS5412568A JP7876177A JP7876177A JPS5412568A JP S5412568 A JPS5412568 A JP S5412568A JP 7876177 A JP7876177 A JP 7876177A JP 7876177 A JP7876177 A JP 7876177A JP S5412568 A JPS5412568 A JP S5412568A
Authority
JP
Japan
Prior art keywords
wafers
semiconductor wafers
aligning method
aligning
providing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7876177A
Other languages
Japanese (ja)
Other versions
JPS5646257B2 (en
Inventor
Tadahiko Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Original Assignee
Tokyo Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Sanyo Electric Co Ltd, Sanyo Electric Co Ltd filed Critical Tokyo Sanyo Electric Co Ltd
Priority to JP7876177A priority Critical patent/JPS5412568A/en
Publication of JPS5412568A publication Critical patent/JPS5412568A/en
Publication of JPS5646257B2 publication Critical patent/JPS5646257B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE: To automate aligning of the second and subsequent wafers after fine adjustment of the first wafer has been finished by providing first, second aligning line portions to semiconductor wafers, and providing a means of raising and moving the wafers and a means of rotating the wafers in the crossing-point direction on the extention of these two line parts.
COPYRIGHT: (C)1979,JPO&Japio
JP7876177A 1977-06-29 1977-06-29 Aligning method of semiconductor wafers Granted JPS5412568A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7876177A JPS5412568A (en) 1977-06-29 1977-06-29 Aligning method of semiconductor wafers

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7876177A JPS5412568A (en) 1977-06-29 1977-06-29 Aligning method of semiconductor wafers

Publications (2)

Publication Number Publication Date
JPS5412568A true JPS5412568A (en) 1979-01-30
JPS5646257B2 JPS5646257B2 (en) 1981-10-31

Family

ID=13670879

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7876177A Granted JPS5412568A (en) 1977-06-29 1977-06-29 Aligning method of semiconductor wafers

Country Status (1)

Country Link
JP (1) JPS5412568A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6084544A (en) * 1983-10-15 1985-05-13 Nec Corp Reduced projection type exposing device

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58173240U (en) * 1982-05-14 1983-11-19 クラリオン株式会社 Semiconductor chip with alignment pattern
JPS60134616A (en) * 1983-12-23 1985-07-17 Toshiba Corp Diaphragm type piezoelectric resonator

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5046486A (en) * 1973-08-31 1975-04-25

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5046486A (en) * 1973-08-31 1975-04-25

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6084544A (en) * 1983-10-15 1985-05-13 Nec Corp Reduced projection type exposing device

Also Published As

Publication number Publication date
JPS5646257B2 (en) 1981-10-31

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