JPS54112171A - Semiconductor device and its manufacture - Google Patents

Semiconductor device and its manufacture

Info

Publication number
JPS54112171A
JPS54112171A JP2011478A JP2011478A JPS54112171A JP S54112171 A JPS54112171 A JP S54112171A JP 2011478 A JP2011478 A JP 2011478A JP 2011478 A JP2011478 A JP 2011478A JP S54112171 A JPS54112171 A JP S54112171A
Authority
JP
Japan
Prior art keywords
film
junction
photoetching
photo resist
powder mixed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2011478A
Other languages
Japanese (ja)
Inventor
Takeshi Yamamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2011478A priority Critical patent/JPS54112171A/en
Publication of JPS54112171A publication Critical patent/JPS54112171A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To stabilize operation characteristics at a high temperature, and also to improve corrosion resistance of a protective film, by stacking and adhering 1st and 2nd glass films, which contain zinc oxide and lead oxide respectively, to the PN- junction exposure surface of a semiconductor substrate.
CONSTITUTION: In P-type Si substrate 1, N-type region 2 is formed by diffusion to make PN junction 3, and onto the entire surface including this, a photo resist with zinc glass powder mixed is rotation-applied by a spinner method and dried to form mixture film 5. While this film 5 is left only on the surface where junction 3 is exposed, the other is removed by photoetching and photo resist mixture film 6 with lead glass powder mixed is adhered to the entire surface including film 5 left. At this time, baking temperatures and thermal expansion coefficient of those films 5 and 6 are made close. Then, photoetching is carried out with film 6 made to remain only on film 5, and the lamination film of them is formed only on the exposure surface of junction 3. In this way, protection is effective against impurity ions by film 5 and against chemicals by film 6.
COPYRIGHT: (C)1979,JPO&Japio
JP2011478A 1978-02-22 1978-02-22 Semiconductor device and its manufacture Pending JPS54112171A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2011478A JPS54112171A (en) 1978-02-22 1978-02-22 Semiconductor device and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2011478A JPS54112171A (en) 1978-02-22 1978-02-22 Semiconductor device and its manufacture

Publications (1)

Publication Number Publication Date
JPS54112171A true JPS54112171A (en) 1979-09-01

Family

ID=12018085

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2011478A Pending JPS54112171A (en) 1978-02-22 1978-02-22 Semiconductor device and its manufacture

Country Status (1)

Country Link
JP (1) JPS54112171A (en)

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