JPS54107682A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPS54107682A
JPS54107682A JP1471778A JP1471778A JPS54107682A JP S54107682 A JPS54107682 A JP S54107682A JP 1471778 A JP1471778 A JP 1471778A JP 1471778 A JP1471778 A JP 1471778A JP S54107682 A JPS54107682 A JP S54107682A
Authority
JP
Japan
Prior art keywords
region
type
regions
source
island
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1471778A
Other languages
Japanese (ja)
Other versions
JPS59985B2 (en
Inventor
Hideaki Sadamatsu
Toyoki Takemoto
Haruyasu Yamada
Michihiro Inoue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP1471778A priority Critical patent/JPS59985B2/en
Publication of JPS54107682A publication Critical patent/JPS54107682A/en
Publication of JPS59985B2 publication Critical patent/JPS59985B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Bipolar Transistors (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE: To establish J-FET of low noise having required transfer conductance with small occupied area, by separating the implanted gate region into islands, forming the surface gate region and the source or drain region clipping it, and connecting the source or drain region each other in the island regions.
CONSTITUTION: The N type layer is epitaxially grown on the P type semiconductor substrate 101, the P type region 112 is formed by diffusion, the epitaxial layer is separated into island region 102, and the P type implanted gate region 103 is formed in the island region 102. Next, only 104a out of the regions 104a to 104c in the island region 102 being the drain region, the N+ type diffusion is made for contact, and in the region 102, the P type source regions 105a and 105b are formed by diffusion. After that, in the region 102 among these regions, the P+ type gate region 106 is provided, and the part between the implanted gate region and it is used as the channel region. Further, oxide film is coated on the entire surface, the window is opened, and the electrodes 109 to 110 for the source, gate and drain are attached.
COPYRIGHT: (C)1979,JPO&Japio
JP1471778A 1978-02-10 1978-02-10 Semiconductor integrated circuit device Expired JPS59985B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1471778A JPS59985B2 (en) 1978-02-10 1978-02-10 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1471778A JPS59985B2 (en) 1978-02-10 1978-02-10 Semiconductor integrated circuit device

Publications (2)

Publication Number Publication Date
JPS54107682A true JPS54107682A (en) 1979-08-23
JPS59985B2 JPS59985B2 (en) 1984-01-10

Family

ID=11868885

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1471778A Expired JPS59985B2 (en) 1978-02-10 1978-02-10 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS59985B2 (en)

Also Published As

Publication number Publication date
JPS59985B2 (en) 1984-01-10

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