JPS54160180A - Semiconductor device and its manufacture - Google Patents

Semiconductor device and its manufacture

Info

Publication number
JPS54160180A
JPS54160180A JP6957378A JP6957378A JPS54160180A JP S54160180 A JPS54160180 A JP S54160180A JP 6957378 A JP6957378 A JP 6957378A JP 6957378 A JP6957378 A JP 6957378A JP S54160180 A JPS54160180 A JP S54160180A
Authority
JP
Japan
Prior art keywords
type
gate
layer
diffusion
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6957378A
Other languages
Japanese (ja)
Inventor
Haruyasu Yamada
Toyoki Takemoto
Michihiro Inoue
Hideaki Sadamatsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP6957378A priority Critical patent/JPS54160180A/en
Publication of JPS54160180A publication Critical patent/JPS54160180A/en
Pending legal-status Critical Current

Links

Landscapes

  • Junction Field-Effect Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE: To minimize the gate serial resistance to enhance the area denisity and at the same time to obtain the necessary transmission conductance in order to realize reduction of the noise, by providing the poly-crystal Si layer connecting to the J- FET on the surface gate of the J-FET and then adding the electrode wiring on the Si layer.
CONSTITUTION: N-type layer 21 is epitaxial-grown on P-type Si substrate 20, and the P-type diffusion region reaching substrate 20 is formed into an island shape with formation of the electrode diffusion layers of P-type source regions 22 and drain region 23 each. Then P--type channel region 24 is formed by the ion implantation, and at the same time N-type region 27 for contact electrode use is formed by diffusion at the bottom part gate of epitaxial layer 21. After this, SiO2 film 24 is coated over the entire surface with the window drilled at the formation area of the surface gate, and then the poly-crystal Si layer containing the N-type impurity is stacked over the entire surface to be then removed except at the surface gate diffusion part. Using the Si layer as the diffusion source, surface gate region 25 is formed, and Al electrodes 31∼33 are attached to the source, the drain and the bottom part gate respectively.
COPYRIGHT: (C)1979,JPO&Japio
JP6957378A 1978-06-08 1978-06-08 Semiconductor device and its manufacture Pending JPS54160180A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6957378A JPS54160180A (en) 1978-06-08 1978-06-08 Semiconductor device and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6957378A JPS54160180A (en) 1978-06-08 1978-06-08 Semiconductor device and its manufacture

Publications (1)

Publication Number Publication Date
JPS54160180A true JPS54160180A (en) 1979-12-18

Family

ID=13406656

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6957378A Pending JPS54160180A (en) 1978-06-08 1978-06-08 Semiconductor device and its manufacture

Country Status (1)

Country Link
JP (1) JPS54160180A (en)

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