JPS5327375A - Production of semiconductor device - Google Patents
Production of semiconductor deviceInfo
- Publication number
- JPS5327375A JPS5327375A JP10231476A JP10231476A JPS5327375A JP S5327375 A JPS5327375 A JP S5327375A JP 10231476 A JP10231476 A JP 10231476A JP 10231476 A JP10231476 A JP 10231476A JP S5327375 A JPS5327375 A JP S5327375A
- Authority
- JP
- Japan
- Prior art keywords
- production
- semiconductor device
- impurity
- injecting
- changing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
- H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Element Separation (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10231476A JPS5327375A (en) | 1976-08-26 | 1976-08-26 | Production of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10231476A JPS5327375A (en) | 1976-08-26 | 1976-08-26 | Production of semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5327375A true JPS5327375A (en) | 1978-03-14 |
JPS5436077B2 JPS5436077B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | 1979-11-07 |
Family
ID=14324122
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10231476A Granted JPS5327375A (en) | 1976-08-26 | 1976-08-26 | Production of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5327375A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2496983A1 (fr) * | 1980-12-23 | 1982-06-25 | Philips Nv | Procede de fabrication par auto-alignement d'un dispositif semiconducteur comportant un igfet de dimension tres faible |
JPS5843563A (ja) * | 1981-08-27 | 1983-03-14 | シ−メンス・アクチエンゲゼルシヤフト | 高度集積cmos電界効果トランジスタ回路の製造方法 |
-
1976
- 1976-08-26 JP JP10231476A patent/JPS5327375A/ja active Granted
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2496983A1 (fr) * | 1980-12-23 | 1982-06-25 | Philips Nv | Procede de fabrication par auto-alignement d'un dispositif semiconducteur comportant un igfet de dimension tres faible |
JPS5843563A (ja) * | 1981-08-27 | 1983-03-14 | シ−メンス・アクチエンゲゼルシヤフト | 高度集積cmos電界効果トランジスタ回路の製造方法 |
Also Published As
Publication number | Publication date |
---|---|
JPS5436077B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | 1979-11-07 |
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