JPS5293278A - Manufacture for mos type semiconductor intergrated circuit - Google Patents

Manufacture for mos type semiconductor intergrated circuit

Info

Publication number
JPS5293278A
JPS5293278A JP987176A JP987176A JPS5293278A JP S5293278 A JPS5293278 A JP S5293278A JP 987176 A JP987176 A JP 987176A JP 987176 A JP987176 A JP 987176A JP S5293278 A JPS5293278 A JP S5293278A
Authority
JP
Japan
Prior art keywords
manufacture
type semiconductor
mos type
intergrated circuit
semiconductor intergrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP987176A
Other languages
English (en)
Japanese (ja)
Inventor
Tomisaburo Okumura
Hiroshi Okazaki
Akira Tsuchiya
Seiji Ueda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP987176A priority Critical patent/JPS5293278A/ja
Priority to DE19772702922 priority patent/DE2702922A1/de
Priority to GB3599/77A priority patent/GB1553533A/en
Priority to US05/763,679 priority patent/US4113533A/en
Priority to CA270,677A priority patent/CA1067210A/en
Priority to FR7702483A priority patent/FR2339954A1/fr
Publication of JPS5293278A publication Critical patent/JPS5293278A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/61—Formation of materials, e.g. in the shape of layers or pillars of insulating materials using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6302—Non-deposition formation processes
    • H10P14/6304—Formation by oxidation, e.g. oxidation of the substrate
    • H10P14/6306—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials
    • H10P14/6308—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials of Group IV semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/053—Field effect transistors fets
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/103—Mask, dual function, e.g. diffusion and oxidation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/105—Masks, metal
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/106—Masks, special
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/117—Oxidation, selective
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/141—Self-alignment coat gate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/911—Differential oxidation and etching

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
JP987176A 1976-01-30 1976-01-30 Manufacture for mos type semiconductor intergrated circuit Pending JPS5293278A (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP987176A JPS5293278A (en) 1976-01-30 1976-01-30 Manufacture for mos type semiconductor intergrated circuit
DE19772702922 DE2702922A1 (de) 1976-01-30 1977-01-25 Verfahren zum herstellen eines metalloxidhalbleiter-bauteils
GB3599/77A GB1553533A (en) 1976-01-30 1977-01-28 Method of making mos device
US05/763,679 US4113533A (en) 1976-01-30 1977-01-28 Method of making a mos device
CA270,677A CA1067210A (en) 1976-01-30 1977-01-28 Method of making mos device
FR7702483A FR2339954A1 (fr) 1976-01-30 1977-01-28 Procede de fabrication de dispositifs mos

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP987176A JPS5293278A (en) 1976-01-30 1976-01-30 Manufacture for mos type semiconductor intergrated circuit

Publications (1)

Publication Number Publication Date
JPS5293278A true JPS5293278A (en) 1977-08-05

Family

ID=11732193

Family Applications (1)

Application Number Title Priority Date Filing Date
JP987176A Pending JPS5293278A (en) 1976-01-30 1976-01-30 Manufacture for mos type semiconductor intergrated circuit

Country Status (6)

Country Link
US (1) US4113533A (ref)
JP (1) JPS5293278A (ref)
CA (1) CA1067210A (ref)
DE (1) DE2702922A1 (ref)
FR (1) FR2339954A1 (ref)
GB (1) GB1553533A (ref)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4179311A (en) * 1977-01-17 1979-12-18 Mostek Corporation Method of stabilizing semiconductor device by converting doped poly-Si to polyoxides
JPS5492175A (en) * 1977-12-29 1979-07-21 Fujitsu Ltd Manufacture of semiconductor device
US4219925A (en) * 1978-09-01 1980-09-02 Teletype Corporation Method of manufacturing a device in a silicon wafer
US4240196A (en) * 1978-12-29 1980-12-23 Bell Telephone Laboratories, Incorporated Fabrication of two-level polysilicon devices
US4343078A (en) * 1979-03-05 1982-08-10 Nippon Electric Co., Ltd. IGFET Forming method
DE2923995C2 (de) * 1979-06-13 1985-11-07 Siemens AG, 1000 Berlin und 8000 München Verfahren zum Herstellen von integrierten MOS-Schaltungen mit MOS-Transistoren und MNOS-Speichertransistoren in Silizium-Gate-Technologie
US5202574A (en) * 1980-05-02 1993-04-13 Texas Instruments Incorporated Semiconductor having improved interlevel conductor insulation
NL187328C (nl) * 1980-12-23 1991-08-16 Philips Nv Werkwijze ter vervaardiging van een halfgeleiderinrichting.
AT387474B (de) * 1980-12-23 1989-01-25 Philips Nv Verfahren zur herstellung einer halbleitervorrichtung
NL8402856A (nl) * 1984-09-18 1986-04-16 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting.
JPS62177909A (ja) * 1986-01-31 1987-08-04 Hitachi Ltd 半導体装置の製造方法
EP0250611B1 (de) * 1986-06-21 1990-12-19 Deutsche ITT Industries GmbH Verfahren zum Entfernen einer strukturierten Maskierungsschicht
IT1215558B (it) * 1987-06-11 1990-02-14 Sgs Microelettronica Spa Procedimento di programmazione per memorie rom e tecnolgia mos con ossido di gate e giunzioni sottili.
US5002369A (en) * 1988-01-11 1991-03-26 Canon Kabushiki Kaisha Nonlinear optical element having electrodes on two side surfaces of nonlinear medium through insulating layers
US5879997A (en) * 1991-05-30 1999-03-09 Lucent Technologies Inc. Method for forming self aligned polysilicon contact
US6780718B2 (en) 1993-11-30 2004-08-24 Stmicroelectronics, Inc. Transistor structure and method for making same
US5798291A (en) * 1995-03-20 1998-08-25 Lg Semicon Co., Ltd. Method of making a semiconductor device with recessed source and drain
US5920779A (en) * 1997-05-21 1999-07-06 United Microelectronics Corp. Differential gate oxide thickness by nitrogen implantation for mixed mode and embedded VLSI circuits
US6153454A (en) * 1997-07-09 2000-11-28 Advanced Micro Devices, Inc. Convex device with selectively doped channel
KR100561970B1 (ko) * 2003-09-25 2006-03-22 동부아남반도체 주식회사 반도체 소자의 제조방법
US11282931B2 (en) * 2019-07-31 2022-03-22 Taiwan Semiconductor Manufacturing Co., Ltd. Memory device and manufacturing method thereof

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5051276A (ref) * 1973-08-06 1975-05-08
JPS5066182A (ref) * 1973-10-12 1975-06-04
JPS5075775A (ref) * 1973-11-06 1975-06-21

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3615873A (en) * 1969-06-03 1971-10-26 Sprague Electric Co Method of stabilizing mos devices
NL7113561A (ref) * 1971-10-02 1973-04-04
JPS5910073B2 (ja) * 1972-10-27 1984-03-06 株式会社日立製作所 シリコン・ゲ−トｍｏｓ型半導体装置の製造方法
US3936859A (en) * 1973-08-06 1976-02-03 Rca Corporation Semiconductor device including a conductor surrounded by an insulator
US3943542A (en) * 1974-11-06 1976-03-09 International Business Machines, Corporation High reliability, low leakage, self-aligned silicon gate FET and method of fabricating same
US3958323A (en) * 1975-04-29 1976-05-25 International Business Machines Corporation Three mask self aligned IGFET fabrication process
US4035198A (en) * 1976-06-30 1977-07-12 International Business Machines Corporation Method of fabricating field effect transistors having self-registering electrical connections between gate electrodes and metallic interconnection lines, and fabrication of integrated circuits containing the transistors

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5051276A (ref) * 1973-08-06 1975-05-08
JPS5066182A (ref) * 1973-10-12 1975-06-04
JPS5075775A (ref) * 1973-11-06 1975-06-21

Also Published As

Publication number Publication date
DE2702922A1 (de) 1977-08-04
FR2339954B1 (ref) 1982-01-29
FR2339954A1 (fr) 1977-08-26
CA1067210A (en) 1979-11-27
GB1553533A (en) 1979-09-26
US4113533A (en) 1978-09-12

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