JPS5263672A - Production of semiconductor device - Google Patents

Production of semiconductor device

Info

Publication number
JPS5263672A
JPS5263672A JP50139862A JP13986275A JPS5263672A JP S5263672 A JPS5263672 A JP S5263672A JP 50139862 A JP50139862 A JP 50139862A JP 13986275 A JP13986275 A JP 13986275A JP S5263672 A JPS5263672 A JP S5263672A
Authority
JP
Japan
Prior art keywords
semiconductor device
production
substrate
doublestructure
fear
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP50139862A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5429341B2 (online.php
Inventor
Masaharu Noyori
Isamu Kitahiro
Hiroaki Fujimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP50139862A priority Critical patent/JPS5263672A/ja
Publication of JPS5263672A publication Critical patent/JPS5263672A/ja
Publication of JPS5429341B2 publication Critical patent/JPS5429341B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9413—Dispositions of bond pads on encapsulations

Landscapes

  • Wire Bonding (AREA)
JP50139862A 1975-11-20 1975-11-20 Production of semiconductor device Granted JPS5263672A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP50139862A JPS5263672A (en) 1975-11-20 1975-11-20 Production of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP50139862A JPS5263672A (en) 1975-11-20 1975-11-20 Production of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5263672A true JPS5263672A (en) 1977-05-26
JPS5429341B2 JPS5429341B2 (online.php) 1979-09-22

Family

ID=15255262

Family Applications (1)

Application Number Title Priority Date Filing Date
JP50139862A Granted JPS5263672A (en) 1975-11-20 1975-11-20 Production of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5263672A (online.php)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6855623B2 (en) * 1999-02-24 2005-02-15 Micron Technology Inc. Recessed tape and method for forming a BGA assembly
JP2009514250A (ja) * 2005-11-01 2009-04-02 アレグロ・マイクロシステムズ・インコーポレーテッド フリップチップ・オン・リード半導体パッケージの方法および装置
EP3300105A1 (de) * 2016-09-26 2018-03-28 Infineon Technologies AG Leistungshalbleitermodul und verfahren zur herstellung eines leistungshalbleitermoduls

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6855623B2 (en) * 1999-02-24 2005-02-15 Micron Technology Inc. Recessed tape and method for forming a BGA assembly
JP2009514250A (ja) * 2005-11-01 2009-04-02 アレグロ・マイクロシステムズ・インコーポレーテッド フリップチップ・オン・リード半導体パッケージの方法および装置
JP2013219369A (ja) * 2005-11-01 2013-10-24 Allegro Microsystems Llc フリップチップ・オン・リード半導体パッケージの方法および装置
EP3300105A1 (de) * 2016-09-26 2018-03-28 Infineon Technologies AG Leistungshalbleitermodul und verfahren zur herstellung eines leistungshalbleitermoduls

Also Published As

Publication number Publication date
JPS5429341B2 (online.php) 1979-09-22

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