JPH11317471A - 高性能ボ―ルグリッドアレイパッケ―ジの最適回路設計レイアウト - Google Patents

高性能ボ―ルグリッドアレイパッケ―ジの最適回路設計レイアウト

Info

Publication number
JPH11317471A
JPH11317471A JP11041955A JP4195599A JPH11317471A JP H11317471 A JPH11317471 A JP H11317471A JP 11041955 A JP11041955 A JP 11041955A JP 4195599 A JP4195599 A JP 4195599A JP H11317471 A JPH11317471 A JP H11317471A
Authority
JP
Japan
Prior art keywords
traces
pair
ball
trace
columns
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11041955A
Other languages
English (en)
Japanese (ja)
Inventor
William P Stearns
ピー．スターンズ ウィリアム
Hassanzadee Nozar
ハッサンザデー ノザール
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of JPH11317471A publication Critical patent/JPH11317471A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49826—Assembling or joining

Landscapes

  • Structure Of Printed Boards (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
JP11041955A 1998-02-19 1999-02-19 高性能ボ―ルグリッドアレイパッケ―ジの最適回路設計レイアウト Pending JPH11317471A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US7529098P 1998-02-19 1998-02-19
US075290 1998-02-19

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2009171214A Division JP5254899B2 (ja) 1998-02-19 2009-07-22 高性能ボールグリッドアレイパッケージの最適回路設計レイアウト

Publications (1)

Publication Number Publication Date
JPH11317471A true JPH11317471A (ja) 1999-11-16

Family

ID=22124740

Family Applications (2)

Application Number Title Priority Date Filing Date
JP11041955A Pending JPH11317471A (ja) 1998-02-19 1999-02-19 高性能ボ―ルグリッドアレイパッケ―ジの最適回路設計レイアウト
JP2009171214A Expired - Lifetime JP5254899B2 (ja) 1998-02-19 2009-07-22 高性能ボールグリッドアレイパッケージの最適回路設計レイアウト

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2009171214A Expired - Lifetime JP5254899B2 (ja) 1998-02-19 2009-07-22 高性能ボールグリッドアレイパッケージの最適回路設計レイアウト

Country Status (2)

Country Link
US (3) US6215184B1 (https=)
JP (2) JPH11317471A (https=)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6372552B1 (en) * 1999-05-25 2002-04-16 Micron Technology, Inc. Semiconductor device, ball grid array connection system, and method of making
US6773965B2 (en) 1999-05-25 2004-08-10 Micron Technology, Inc. Semiconductor device, ball grid array connection system, and method of making
WO2005074336A3 (en) * 2004-01-26 2005-10-06 Litton Systems Inc Multilayered circuit board for high-speed, differential signals
WO2015027180A1 (en) * 2013-08-23 2015-02-26 Molex Incorporated Led module

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US6285558B1 (en) * 1998-09-25 2001-09-04 Intelect Communications, Inc. Microprocessor subsystem module for PCB bottom-side BGA installation
JP3610262B2 (ja) * 1999-07-22 2005-01-12 新光電気工業株式会社 多層回路基板及び半導体装置
JP2002170844A (ja) * 2000-12-04 2002-06-14 Oki Electric Ind Co Ltd 半導体装置
TW200408091A (en) * 2001-11-13 2004-05-16 Koninkl Philips Electronics Nv Device for shielding transmission lines from ground or power supply
US6686666B2 (en) 2002-05-16 2004-02-03 Intel Corporation Breaking out signals from an integrated circuit footprint
US20040091027A1 (en) * 2002-11-07 2004-05-13 Booth Bradley J. System, method and device for autonegotiation
US7720135B2 (en) * 2002-11-07 2010-05-18 Intel Corporation System, method and device for autonegotiation
US6933596B2 (en) * 2003-07-01 2005-08-23 Northrop Grumman Corporation Ultra wideband BGA
US7038319B2 (en) * 2003-08-20 2006-05-02 International Business Machines Corporation Apparatus and method to reduce signal cross-talk
JP4425044B2 (ja) * 2004-04-13 2010-03-03 新光電気工業株式会社 半導体パッケージにおける自動配線方法および装置ならびに自動識別装置
US20060185895A1 (en) * 2005-02-24 2006-08-24 Navinchandra Kalidas Universal pattern of contact pads for semiconductor reflow interconnections
CN100574552C (zh) * 2005-08-12 2009-12-23 鸿富锦精密工业（深圳）有限公司 印刷电路板
US8307265B2 (en) * 2009-03-09 2012-11-06 Intel Corporation Interconnection techniques
US8370704B2 (en) * 2009-03-09 2013-02-05 Intel Corporation Cable interconnection techniques
US8379710B2 (en) 2009-03-10 2013-02-19 Intel Corporation Transmitter control in communication systems
KR20130125036A (ko) * 2012-05-08 2013-11-18 삼성전자주식회사 시스템 온 칩, 이의 동작 방법, 및 이를 포함하는 시스템
EP2866532A4 (en) * 2012-09-07 2016-03-09 Fujikura Ltd CONNECTION TABLE
KR102245132B1 (ko) 2014-05-14 2021-04-28 삼성전자 주식회사 트레이스를 가지는 인쇄회로기판 및 볼 그리드 어레이 패키지
KR102339899B1 (ko) 2014-12-12 2021-12-15 삼성전자주식회사 반도체 패키지, 모듈 기판 및 이를 포함하는 반도체 패키지 모듈

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6390865A (ja) * 1986-10-03 1988-04-21 Nec Corp 電界効果トランジスタの製造方法
JPH02240994A (ja) * 1989-03-14 1990-09-25 Toshiba Corp 信号配線基板
JPH1012667A (ja) * 1996-03-20 1998-01-16 Lsi Logic Corp パッケージ層の数を削減したフリップチップ・パッケージ

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JPH0717155Y2 (ja) * 1986-12-04 1995-04-19 日本電気株式会社 Ｌｓｉ用ケ−ス
EP0596075B1 (en) * 1992-05-15 2001-08-22 Irvine Sensors Corporation Non-conductive end layer for integrated stack of ic chips
US5729894A (en) * 1992-07-21 1998-03-24 Lsi Logic Corporation Method of assembling ball bump grid array semiconductor packages
EP0582052A1 (en) * 1992-08-06 1994-02-09 Motorola, Inc. Low profile overmolded semiconductor device and method for making the same
US5612576A (en) * 1992-10-13 1997-03-18 Motorola Self-opening vent hole in an overmolded semiconductor device
US5397921A (en) * 1993-09-03 1995-03-14 Advanced Semiconductor Assembly Technology Tab grid array
US5467252A (en) * 1993-10-18 1995-11-14 Motorola, Inc. Method for plating using nested plating buses and semiconductor device having the same
US5563446A (en) * 1994-01-25 1996-10-08 Lsi Logic Corporation Surface mount peripheral leaded and ball grid array package
US5813881A (en) * 1994-02-08 1998-09-29 Prolinx Labs Corporation Programmable cable and cable adapter using fuses and antifuses
JP2967697B2 (ja) * 1994-11-22 1999-10-25 ソニー株式会社 リードフレームの製造方法と半導体装置の製造方法
JP3362545B2 (ja) * 1995-03-09 2003-01-07 ソニー株式会社 半導体装置の製造方法
US5844168A (en) * 1995-08-01 1998-12-01 Minnesota Mining And Manufacturing Company Multi-layer interconnect sutructure for ball grid arrays
JP3123638B2 (ja) * 1995-09-25 2001-01-15 株式会社三井ハイテック 半導体装置
TW353223B (en) * 1995-10-10 1999-02-21 Acc Microelectronics Corp Semiconductor board providing high signal pin utilization
US5744383A (en) * 1995-11-17 1998-04-28 Altera Corporation Integrated circuit package fabrication method
JP3207738B2 (ja) * 1996-01-15 2001-09-10 株式会社東芝 樹脂封止型半導体装置及びその製造方法
US5729433A (en) * 1996-01-30 1998-03-17 Micromodule Systems, Inc. Multiple chip module assembly for top of mother board
US6169329B1 (en) * 1996-04-02 2001-01-02 Micron Technology, Inc. Semiconductor devices having interconnections using standardized bonding locations and methods of designing
KR19980020726A (ko) * 1996-09-11 1998-06-25 김광호 칩 스케일의 볼 그리드 어레이 패키지 및 그의 제조 방법
JP2976917B2 (ja) * 1997-03-31 1999-11-10 日本電気株式会社 半導体装置
US6020637A (en) 1997-05-07 2000-02-01 Signetics Kp Co., Ltd. Ball grid array semiconductor package
US6160705A (en) 1997-05-09 2000-12-12 Texas Instruments Incorporated Ball grid array package and method using enhanced power and ground distribution circuitry
US5808873A (en) * 1997-05-30 1998-09-15 Motorola, Inc. Electronic component assembly having an encapsulation material and method of forming the same
US6121678A (en) * 1997-12-19 2000-09-19 Stmicroelectronics, Inc. Wrap-around interconnect for fine pitch ball grid array
US6054767A (en) * 1998-01-13 2000-04-25 Lsi Logic Corp. Programmable substrate for array-type packages
US6075710A (en) * 1998-02-11 2000-06-13 Express Packaging Systems, Inc. Low-cost surface-mount compatible land-grid array (LGA) chip scale package (CSP) for packaging solder-bumped flip chips

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6390865A (ja) * 1986-10-03 1988-04-21 Nec Corp 電界効果トランジスタの製造方法
JPH02240994A (ja) * 1989-03-14 1990-09-25 Toshiba Corp 信号配線基板
JPH1012667A (ja) * 1996-03-20 1998-01-16 Lsi Logic Corp パッケージ層の数を削減したフリップチップ・パッケージ

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6372552B1 (en) * 1999-05-25 2002-04-16 Micron Technology, Inc. Semiconductor device, ball grid array connection system, and method of making
US6773965B2 (en) 1999-05-25 2004-08-10 Micron Technology, Inc. Semiconductor device, ball grid array connection system, and method of making
US7091622B2 (en) 1999-05-25 2006-08-15 Micron Technology, Inc. Semiconductor device, ball grid array connection system, and method of making
WO2005074336A3 (en) * 2004-01-26 2005-10-06 Litton Systems Inc Multilayered circuit board for high-speed, differential signals
US7057115B2 (en) 2004-01-26 2006-06-06 Litton Systems, Inc. Multilayered circuit board for high-speed, differential signals
WO2015027180A1 (en) * 2013-08-23 2015-02-26 Molex Incorporated Led module
US9829159B2 (en) 2013-08-23 2017-11-28 Molex, Llc LED module
US10100982B2 (en) 2013-08-23 2018-10-16 Molex, Llc LED module
US10393320B2 (en) 2013-08-23 2019-08-27 Molex, Llc Method of forming a component module

Also Published As

Publication number Publication date
US6215184B1 (en) 2001-04-10
US7611981B1 (en) 2009-11-03
JP2009239318A (ja) 2009-10-15
JP5254899B2 (ja) 2013-08-07
US8039320B2 (en) 2011-10-18
US20090170240A1 (en) 2009-07-02

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