JPH11232868A - 半導体記憶集積回路 - Google Patents
半導体記憶集積回路Info
- Publication number
- JPH11232868A JPH11232868A JP10044353A JP4435398A JPH11232868A JP H11232868 A JPH11232868 A JP H11232868A JP 10044353 A JP10044353 A JP 10044353A JP 4435398 A JP4435398 A JP 4435398A JP H11232868 A JPH11232868 A JP H11232868A
- Authority
- JP
- Japan
- Prior art keywords
- memory cell
- flip
- pair
- flop circuit
- channel mos
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 26
- 230000005540 biological transmission Effects 0.000 claims abstract description 15
- 230000000295 complement effect Effects 0.000 claims abstract description 13
- 239000003990 capacitor Substances 0.000 claims description 15
- 239000011159 matrix material Substances 0.000 claims description 4
- 230000010354 integration Effects 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 230000003321 amplification Effects 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 238000003199 nucleic acid amplification method Methods 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 230000003111 delayed effect Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
- G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
- G11C7/065—Differential amplifiers of latching type
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
- Semiconductor Memories (AREA)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10044353A JPH11232868A (ja) | 1998-02-10 | 1998-02-10 | 半導体記憶集積回路 |
| US09/241,748 US5943279A (en) | 1998-02-10 | 1999-02-01 | Semiconductor memory integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10044353A JPH11232868A (ja) | 1998-02-10 | 1998-02-10 | 半導体記憶集積回路 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH11232868A true JPH11232868A (ja) | 1999-08-27 |
| JPH11232868A5 JPH11232868A5 (enExample) | 2005-08-25 |
Family
ID=12689161
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10044353A Pending JPH11232868A (ja) | 1998-02-10 | 1998-02-10 | 半導体記憶集積回路 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US5943279A (enExample) |
| JP (1) | JPH11232868A (enExample) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004281736A (ja) * | 2003-03-17 | 2004-10-07 | Nec Electronics Corp | 半導体記憶装置 |
| JPWO2019106989A1 (ja) * | 2017-11-28 | 2020-12-17 | ソニーセミコンダクタソリューションズ株式会社 | 表示装置及び電子機器 |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003223788A (ja) * | 2002-01-29 | 2003-08-08 | Hitachi Ltd | 半導体集積回路装置 |
| US7035132B2 (en) * | 2002-04-30 | 2006-04-25 | Stmicroelectronics Pvt. Ltd | Memory architecture for increased speed and reduced power consumption |
| US6888187B2 (en) * | 2002-08-26 | 2005-05-03 | International Business Machines Corporation | DRAM cell with enhanced SER immunity |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6116099A (ja) * | 1984-06-29 | 1986-01-24 | Sharp Corp | ダイナミック型半導体記憶装置 |
| JPS61240497A (ja) * | 1985-04-17 | 1986-10-25 | Sanyo Electric Co Ltd | 半導体メモリ |
| JPS6265295A (ja) * | 1985-09-13 | 1987-03-24 | Sanyo Electric Co Ltd | ダイナミツクメモリ |
| US5293563A (en) * | 1988-12-29 | 1994-03-08 | Sharp Kabushiki Kaisha | Multi-level memory cell with increased read-out margin |
| GB9007789D0 (en) * | 1990-04-06 | 1990-06-06 | Foss Richard C | Method for dram sensing current control |
| US5684736A (en) * | 1996-06-17 | 1997-11-04 | Nuram Technology, Inc. | Multilevel memory cell sense amplifier system |
| JP3720934B2 (ja) * | 1996-12-17 | 2005-11-30 | 富士通株式会社 | 半導体記憶装置とデータ読み出し及び書き込み方法 |
-
1998
- 1998-02-10 JP JP10044353A patent/JPH11232868A/ja active Pending
-
1999
- 1999-02-01 US US09/241,748 patent/US5943279A/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004281736A (ja) * | 2003-03-17 | 2004-10-07 | Nec Electronics Corp | 半導体記憶装置 |
| JPWO2019106989A1 (ja) * | 2017-11-28 | 2020-12-17 | ソニーセミコンダクタソリューションズ株式会社 | 表示装置及び電子機器 |
Also Published As
| Publication number | Publication date |
|---|---|
| US5943279A (en) | 1999-08-24 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20050209 |
|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20050209 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20071218 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20071225 |
|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20080513 |