JPH11232868A5 - - Google Patents
Info
- Publication number
- JPH11232868A5 JPH11232868A5 JP1998044353A JP4435398A JPH11232868A5 JP H11232868 A5 JPH11232868 A5 JP H11232868A5 JP 1998044353 A JP1998044353 A JP 1998044353A JP 4435398 A JP4435398 A JP 4435398A JP H11232868 A5 JPH11232868 A5 JP H11232868A5
- Authority
- JP
- Japan
- Prior art keywords
- flip
- pair
- memory cell
- flop circuit
- cell column
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10044353A JPH11232868A (ja) | 1998-02-10 | 1998-02-10 | 半導体記憶集積回路 |
| US09/241,748 US5943279A (en) | 1998-02-10 | 1999-02-01 | Semiconductor memory integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10044353A JPH11232868A (ja) | 1998-02-10 | 1998-02-10 | 半導体記憶集積回路 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH11232868A JPH11232868A (ja) | 1999-08-27 |
| JPH11232868A5 true JPH11232868A5 (enExample) | 2005-08-25 |
Family
ID=12689161
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10044353A Pending JPH11232868A (ja) | 1998-02-10 | 1998-02-10 | 半導体記憶集積回路 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US5943279A (enExample) |
| JP (1) | JPH11232868A (enExample) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003223788A (ja) * | 2002-01-29 | 2003-08-08 | Hitachi Ltd | 半導体集積回路装置 |
| US7035132B2 (en) * | 2002-04-30 | 2006-04-25 | Stmicroelectronics Pvt. Ltd | Memory architecture for increased speed and reduced power consumption |
| US6888187B2 (en) * | 2002-08-26 | 2005-05-03 | International Business Machines Corporation | DRAM cell with enhanced SER immunity |
| JP2004281736A (ja) * | 2003-03-17 | 2004-10-07 | Nec Electronics Corp | 半導体記憶装置 |
| TWI797162B (zh) * | 2017-11-28 | 2023-04-01 | 日商索尼半導體解決方案公司 | 顯示裝置及電子機器 |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6116099A (ja) * | 1984-06-29 | 1986-01-24 | Sharp Corp | ダイナミック型半導体記憶装置 |
| JPS61240497A (ja) * | 1985-04-17 | 1986-10-25 | Sanyo Electric Co Ltd | 半導体メモリ |
| JPS6265295A (ja) * | 1985-09-13 | 1987-03-24 | Sanyo Electric Co Ltd | ダイナミツクメモリ |
| US5293563A (en) * | 1988-12-29 | 1994-03-08 | Sharp Kabushiki Kaisha | Multi-level memory cell with increased read-out margin |
| GB9007789D0 (en) * | 1990-04-06 | 1990-06-06 | Foss Richard C | Method for dram sensing current control |
| US5684736A (en) * | 1996-06-17 | 1997-11-04 | Nuram Technology, Inc. | Multilevel memory cell sense amplifier system |
| JP3720934B2 (ja) * | 1996-12-17 | 2005-11-30 | 富士通株式会社 | 半導体記憶装置とデータ読み出し及び書き込み方法 |
-
1998
- 1998-02-10 JP JP10044353A patent/JPH11232868A/ja active Pending
-
1999
- 1999-02-01 US US09/241,748 patent/US5943279A/en not_active Expired - Lifetime
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