JPH11134242A5 - - Google Patents

Info

Publication number
JPH11134242A5
JPH11134242A5 JP1998248261A JP24826198A JPH11134242A5 JP H11134242 A5 JPH11134242 A5 JP H11134242A5 JP 1998248261 A JP1998248261 A JP 1998248261A JP 24826198 A JP24826198 A JP 24826198A JP H11134242 A5 JPH11134242 A5 JP H11134242A5
Authority
JP
Japan
Prior art keywords
data
buffer
memory means
repeat
data sequence
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
JP1998248261A
Other languages
English (en)
Japanese (ja)
Other versions
JPH11134242A (ja
Filing date
Publication date
Priority claimed from EP97115982A external-priority patent/EP0864977B1/en
Application filed filed Critical
Publication of JPH11134242A publication Critical patent/JPH11134242A/ja
Publication of JPH11134242A5 publication Critical patent/JPH11134242A5/ja
Ceased legal-status Critical Current

Links

JP10248261A 1997-09-13 1998-09-02 メモリ手段にアクセスするための装置 Ceased JPH11134242A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP97115982A EP0864977B1 (en) 1997-09-13 1997-09-13 Memory latency compensation
EP97115982.7 1997-09-13

Publications (2)

Publication Number Publication Date
JPH11134242A JPH11134242A (ja) 1999-05-21
JPH11134242A5 true JPH11134242A5 (enExample) 2005-11-04

Family

ID=8227349

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10248261A Ceased JPH11134242A (ja) 1997-09-13 1998-09-02 メモリ手段にアクセスするための装置

Country Status (4)

Country Link
US (1) US6351793B2 (enExample)
EP (1) EP0864977B1 (enExample)
JP (1) JPH11134242A (enExample)
DE (1) DE69700328T2 (enExample)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2829253A1 (fr) * 2001-08-31 2003-03-07 Koninkl Philips Electronics Nv Controle d'acces dynamique d'une fonction a ressource collective
DE10159165B4 (de) 2001-12-03 2007-02-08 Agilent Technologies, Inc. (n.d.Ges.d.Staates Delaware), Palo Alto Vorrichtung zum Messen und/oder Kalibrieren eines Testkopfes
EP1255386B1 (en) 2001-12-05 2007-10-24 Agilent Technologies, Inc. Line equaliser for compensation of droop effect
DE60300141T2 (de) 2003-02-25 2005-11-03 Agilent Technologies, Inc., Palo Alto Aufspüren eines Signalübergangs
US7104346B2 (en) * 2003-03-25 2006-09-12 Schaffner Walter E Power wheelchair
DE60308844T2 (de) 2003-06-17 2007-03-01 Agilent Technologies, Inc., Palo Alto Sigma-Delta-Modulator mit Pulsbreitenmodulations-Ausgang
EP1600784A1 (en) 2004-05-03 2005-11-30 Agilent Technologies, Inc. Serial/parallel interface for an integrated circuit
DE602004017440D1 (de) 2004-06-24 2008-12-11 Verigy Pte Ltd Singapore Schnelle Synchronisierung einem Anzahl von digitale Takten
DE602004021178D1 (de) 2004-06-24 2009-07-02 Verigy Pte Ltd Singapore Taktsynthese pro Stift
ATE441120T1 (de) 2004-07-07 2009-09-15 Verigy Pte Ltd Singapore Auswertung eines ausgangssignals eines gerade geprüften bausteins
EP1624577B1 (en) 2004-08-06 2008-07-23 Verigy (Singapore) Pte. Ltd. Improved analog signal generation using a delta-sigma modulator
WO2006092173A1 (en) 2005-03-02 2006-09-08 Agilent Technologies, Inc. Analog signal test using a-priori information
DE602005009133D1 (de) 2005-03-11 2008-10-02 Verigy Pte Ltd Singapore Fehlererkennung in komprimierten Daten
EP1875650A1 (en) 2005-04-29 2008-01-09 Verigy (Singapore) Pte. Ltd. Communication circuit for a bi-directonal data transmission
WO2010054669A1 (en) 2008-11-11 2010-05-20 Verigy (Singapore) Pte.Ltd. Re-configurable test circuit, method for operating an automated test equipment, apparatus, method and computer program for setting up an automated test equipment
JP5873275B2 (ja) * 2011-09-12 2016-03-01 キヤノン株式会社 描画装置及び物品の製造方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5847741B2 (ja) * 1978-03-29 1983-10-24 日本電信電話株式会社 パタ−ン発生器
CA1251575A (en) * 1985-12-18 1989-03-21 A. Keith Jeffrey Automatic test system having a "true tester-per-pin" architecture
US5317718A (en) * 1990-03-27 1994-05-31 Digital Equipment Corporation Data processing system and method with prefetch buffers
JPH07253922A (ja) * 1994-03-14 1995-10-03 Texas Instr Japan Ltd アドレス生成回路
US5890207A (en) * 1996-11-27 1999-03-30 Emc Corporation High performance integrated cached storage device
US5890219A (en) * 1996-11-27 1999-03-30 Emc Corporation Redundant writing of data to cached storage system
US6112266A (en) * 1998-01-22 2000-08-29 Pc-Tel, Inc. Host signal processing modem using a software circular buffer in system memory and direct transfers of samples to maintain a communication signal

Similar Documents

Publication Publication Date Title
JPH11134242A5 (enExample)
DE69526431D1 (de) Eine synchrone nand-dram-speicherarchitektur
JP2006507602A5 (enExample)
KR970007653A (ko) 외부기억장치 및 그의 메모리 액세스 제어방법
KR20050092378A (ko) 동적 메모리를 위한 재생 포트
US6351793B2 (en) Memory latency compensation
JP2008511904A (ja) 単方向データバスを有するメモリシステムおよび方法
US20020004880A1 (en) Method for controlling a multibank memory device
JPH0433029A (ja) メモリ装置とその駆動方法
KR960011442A (ko) 벡터 모듈 테이블을 사용하는 자동 테스트 장치용 메모리 아키텍처
CN100456679C (zh) 供双缓存tdm交换机使用的数据存储器扩展
JPH0256760B2 (enExample)
US6138214A (en) Synchronous dynamic random access memory architecture for sequential burst mode
JPH02177190A (ja) メモリ装置
JPH04293134A (ja) メモリ・アクセス制御装置
EP1271543A3 (en) Method and system for fast memory access
JP2002333464A5 (enExample)
JP2793184B2 (ja) 半導体記憶装置
JP2850366B2 (ja) バッファメモリ回路
JPH04278651A (ja) 主記憶装置
JP4379948B2 (ja) ディスクドライブインターフェース装置
JPH07281992A (ja) Ｄｍａコントローラ
JPS6244352B2 (enExample)
KR100317323B1 (ko) 플래쉬 메모리 장치
JP5046444B2 (ja) 電話交換装置及びそれに用いる機能制御コード記録方式